AMDGPU: Add definitions for scalar store instructions

Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

llvm-svn: 285463

1 files changed, 5 insertions, 0 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index c6844d36479..416772199da 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -105,6 +105,7 @@ protected:
   bool Has16BitInsts;
   bool HasMovrel;
   bool HasVGPRIndexMode;
+  bool HasScalarStores;
   bool FlatAddressSpace;
   bool R600ALUInst;
   bool CaymanISA;
@@ -527,6 +528,10 @@ public:
     return getGeneration() >= VOLCANIC_ISLANDS;
   }
 
+  bool hasScalarStores() const {
+    return HasScalarStores;
+  }
+
   bool enableSIScheduler() const {
     return EnableSIScheduler;
   }