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* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-154-8/+15
* AMDGPU: Try to commute sub of boolean extMatt Arsenault2019-11-151-3/+26
* GlobalISel: Lower s1 source G_SITOFP/G_UITOFPMatt Arsenault2019-11-153-48/+2
* Sink all InitializePasses.h includesReid Kleckner2019-11-1324-23/+46
* AMDGPU: Extend add x, (ext setcc) combine to subMatt Arsenault2019-11-131-0/+22
* AMDGPU: Switch backend default max workgroup size to 1024Matt Arsenault2019-11-131-7/+1
* AMDGPU Reduce reported maximum group size to 1024Matt Arsenault2019-11-131-1/+2
* AMDGPU/SI: make ~SIScheduleBlockCreator trivialFangrui Song2019-11-112-6/+2
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-114-8/+8
* Remove duplicate MemVT to fix shadow variable warning. NFCI.Simon Pilgrim2019-11-091-1/+0
* Remove superfluous break after return. NFC.Simon Pilgrim2019-11-091-2/+0
* Fix shadow variable warning by reducing scope of CC/InverseCC CondCodes. NFCI.Simon Pilgrim2019-11-091-3/+3
* [AMDGPU][MC] Corrected src0 for v_movrelsd_b32 and v_movrelsd_2_b32Dmitry Preobrazhensky2019-11-081-6/+8
* [AMDGPU] Fix bug introduced in 47a5c36b37f0dfukalov2019-11-071-1/+1
* AMDGPU: Select global atomicrmw faddMatt Arsenault2019-11-065-13/+21
* [AMDGPU] Add handling of 160 bit registers in analyzeResourceUsageStanislav Mekhanoshin2019-11-061-0/+7
* [AMDGPU] Improve code size cost model (part 2)dfukalov2019-11-061-18/+98
* [AMDGPU] Add missing flags to DS_RealStanislav Mekhanoshin2019-11-051-0/+2
* [AMDGPU] Removed dead code from R600ISelLowering.cppStanislav Mekhanoshin2019-11-051-6/+1
* [AMDGPU] Removed dead code handling M0CopyRegStanislav Mekhanoshin2019-11-051-14/+0
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-055-11/+11
* [AMDGPU] return Fail instead of SolfFail from addOperand()Stanislav Mekhanoshin2019-11-051-1/+1
* [AMDGPU] Added assert in SIFoldOperands before ptr use. NFC.Stanislav Mekhanoshin2019-11-041-0/+1
* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-0411-38/+46
* [SIMachineScheduler] Fixed ''then' statement is equivalent to the 'else' stat...Dávid Bolvanský2019-11-031-6/+1
* [SILoadStoreOptimizer] Fixed typo. NFCI.Dávid Bolvanský2019-11-031-1/+1
* [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.Michael Liao2019-11-011-0/+3
* AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault2019-11-013-6/+33
* DAG: Add DAG argument to isFPExtFoldableMatt Arsenault2019-10-312-3/+4
* DAG: Add new control for ISD::FMAD formationMatt Arsenault2019-10-312-0/+16
* AMDGPU: Simplify getAddressSpace callsMatt Arsenault2019-10-314-11/+12
* AMDGPU: Disallow spill folding with m0 copiesMatt Arsenault2019-10-302-0/+42
* AMDGPU: Don't fold S_NOPs with implicit operandsMatt Arsenault2019-10-301-1/+3
* [AMDGPU] Simplify VCCZ bug handlingJay Foad2019-10-301-5/+1
* [AMDGPU] Consolidate one more getGeneration checkJay Foad2019-10-301-1/+1
* AMDGPU/GlobalISel: Legalize FDIV32Austin Kerbow2019-10-292-0/+101
* AMDGPU: Make VReg_1 only include 1 artificial registerMatt Arsenault2019-10-281-1/+15
* AMDGPU: Avoid overwriting saved PCAustin Kerbow2019-10-281-6/+20
* [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64Dmitry Preobrazhensky2019-10-281-2/+6
* [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.cdevadas2019-10-261-90/+89
* [AMDGPU] Enable SGPR copy foldingStanislav Mekhanoshin2019-10-252-14/+11
* [AMDGPU] Fixed asan failure in SIFoldOperandsStanislav Mekhanoshin2019-10-251-3/+4
* AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHGMatt Arsenault2019-10-259-76/+97
* AMDGPU: Fix the broken dominator tree when creating waterfall loop for resour...Changpeng Fang2019-10-251-2/+2
* [AMDGPU] Fold AGPR reg_sequence initializersStanislav Mekhanoshin2019-10-251-22/+131
* [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (wh...vpykhtin2019-10-251-1/+2
* AMDGPU/GlobalISel: Legalize FDIV16Austin Kerbow2019-10-252-0/+41
* [AMDGPU] Fix mfma scheduling crashStanislav Mekhanoshin2019-10-241-1/+6
* [NFC] Remove redundant linesdfukalov2019-10-241-4/+0
* [AMDGPU] Skip additional folding on the same operand.Michael Liao2019-10-241-7/+19
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