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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
* sdsched: Use the right heuristics when -mcpu is not provided and we have no i...Andrew Trick2012-06-051-13/+12
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-1/+1
* Mark some static arrays as const.Craig Topper2012-05-241-1/+1
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-5/+6
* Source order scheduler should not preschedule nodes with multiple uses. rdar:...Evan Cheng2012-03-221-7/+11
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-6/+6
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-12/+12
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+6
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-1/+1
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
* Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://p...Eli Friedman2011-12-071-1/+8
* Fix an assertion in the scheduler. PR11386. No testcase included because it...Eli Friedman2011-12-071-3/+2
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-2/+2
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re...Pete Cooper2011-11-151-0/+5
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-101-1/+5
* Speculatively revert commit 144124 (djg) in the hope that the 32 bitDuncan Sands2011-11-091-13/+3
* Add a hack to the scheduler to disable pseudo-two-address dependencies inDan Gohman2011-11-081-3/+13
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-031-2/+181
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-291-163/+2
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-281-2/+163
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-134/+0
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-0/+134
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-4/+4
* Remove a now dead function, fixing -Wunused-function warnings fromChandler Carruth2011-10-211-20/+0
* Delete the list-tdrr scheduler. Top-down schedulers are going awayDan Gohman2011-10-201-203/+11
* PreRA scheduler should avoid cloning compares.Andrew Trick2011-09-011-1/+35
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-20/+20
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-271-7/+3
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-1/+2
* Fix some trailing issues from my introduction of MVT::untyped and its use for...Owen Anderson2011-06-211-1/+11
* Remove unused but set variables.Benjamin Kramer2011-06-181-2/+0
* Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson2011-06-151-9/+39
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-151-14/+42
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-261-1/+42
* Fix typoEvan Cheng2011-04-261-1/+1
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-141-13/+53
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat...Andrew Trick2011-04-131-110/+176
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-121-177/+111
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-121-111/+177
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-4/+55
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
* whitespaceAndrew Trick2011-03-231-2/+2
* Grammar-o.Eric Christopher2011-03-211-1/+1
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