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path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-051-0/+4
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Handle sub-register operands in recomputeRegClass().Jakob Stoklund Olesen2011-12-191-4/+6
| | | | | | | | | | | Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. llvm-svn: 146874
* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-121-4/+1
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. llvm-svn: 141836
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-4/+3
| | | | | | It will soon need the context. llvm-svn: 140896
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-221-4/+6
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. llvm-svn: 140339
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-091-1/+32
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. llvm-svn: 137123
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-291-1/+2
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. llvm-svn: 136532
* Remove RegClass2VRegMap from MachineRegisterInfo.Evan Cheng2011-06-271-14/+0
| | | | llvm-svn: 133967
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-8/+1
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-1/+8
| | | | llvm-svn: 124611
* Use IndexedMap for MachineRegisterInfo as well. No functional change.Jakob Stoklund Olesen2011-01-091-19/+22
| | | | llvm-svn: 123106
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-061-0/+14
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. llvm-svn: 115875
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-101-6/+3
| | | | llvm-svn: 108062
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-241-14/+25
| | | | | | and to clean up unused incoming physregs from the live-in list. llvm-svn: 106805
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
| | | | | | std::vector. llvm-svn: 106298
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Remove unused function.Benjamin Kramer2010-05-291-69/+0
| | | | llvm-svn: 105100
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-291-30/+12
| | | | llvm-svn: 105095
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-241-0/+9
| | | | llvm-svn: 104560
* Add a utility function for conservatively clearing kill flags, and makeDan Gohman2010-05-131-0/+9
| | | | | | use of it in MachineCSE. llvm-svn: 103726
* Silence warningJakob Stoklund Olesen2010-05-111-1/+1
| | | | llvm-svn: 103508
* Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen2010-05-111-0/+9
| | | | | | | | closure after allocating all blocks. Add a few more test cases for -regalloc=fast. llvm-svn: 103500
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng2010-04-281-28/+9
| | | | | | instructions for function arguments early and insert them after instruction selection is done. llvm-svn: 102554
* Insert dbg_value instructions for function entry block liveins (i.e. ↵Evan Cheng2010-04-261-1/+30
| | | | | | function arguments). llvm-svn: 102368
* Move the code for initialing the entry block livein set out ofDan Gohman2010-04-141-0/+5
| | | | | | SelectionDAGISel. llvm-svn: 101258
* Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman2010-04-141-0/+106
| | | | llvm-svn: 101254
* Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman2010-04-131-0/+14
| | | | llvm-svn: 101145
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-031-0/+13
| | | | llvm-svn: 97663
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-5/+3
| | | | llvm-svn: 82812
* Part 1.Evan Cheng2009-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-0/+2
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
| | | | llvm-svn: 69126
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-081-0/+18
| | | | llvm-svn: 60684
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
| | | | llvm-svn: 57844
* Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman2008-07-071-0/+3
| | | | | | their cleanup code. llvm-svn: 53194
* Added debugging routine dumpUses.Evan Cheng2008-02-131-0/+8
| | | | llvm-svn: 47042
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-5/+5
| | | | llvm-svn: 46930
* switch the register iterator to act more like hte LLVM value iterator: ↵Chris Lattner2008-01-011-2/+16
| | | | | | | | | | | dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. llvm-svn: 45482
* Add a trivial but handy function to efficiently return the machine Chris Lattner2008-01-011-0/+15
| | | | | | instruction that defines the specified vreg. Crazy. llvm-svn: 45480
* Implement automatically updated def/use lists for all MachineInstr register Chris Lattner2008-01-011-1/+27
| | | | | | | operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. llvm-svn: 45477
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-0/+20
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
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