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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-09 16:46:27 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-09 16:46:27 +0000 |
commit | da96006975eaf438ecec4c245a0b521c08ea594d (patch) | |
tree | f2896717f76d2b9295a6416d500435d97cc8d075 /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
parent | 7874310ba116a6d100316afa5093a2698aca7de5 (diff) | |
download | bcm5719-llvm-da96006975eaf438ecec4c245a0b521c08ea594d.tar.gz bcm5719-llvm-da96006975eaf438ecec4c245a0b521c08ea594d.zip |
Move CalculateRegClass to MRI::recomputeRegClass.
This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.
llvm-svn: 137123
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineRegisterInfo.cpp | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index 62dd5768785..d7953896be1 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Support/CommandLine.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) @@ -61,6 +61,37 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg, return NewRC; } +bool +MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { + const TargetInstrInfo *TII = TM.getInstrInfo(); + const TargetRegisterInfo *TRI = TM.getRegisterInfo(); + const TargetRegisterClass *OldRC = getRegClass(Reg); + const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); + + // Stop early if there is no room to grow. + if (NewRC == OldRC) + return false; + + // Accumulate constraints from all uses. + for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; + ++I) { + // TRI doesn't have accurate enough information to model this yet. + if (I.getOperand().getSubReg()) + return false; + // Inline asm instuctions don't remember their constraints. + if (I->isInlineAsm()) + return false; + const TargetRegisterClass *OpRC = + TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI); + if (OpRC) + NewRC = getCommonSubClass(NewRC, OpRC); + if (!NewRC || NewRC == OldRC) + return false; + } + setRegClass(Reg, NewRC); + return true; +} + /// createVirtualRegister - Create and return a new virtual register in the /// function with the specified register class. /// |