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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-30 22:18:51 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-30 22:18:51 +0000 |
| commit | 1352be2bd3249fcb0225ff41939973078756aff2 (patch) | |
| tree | 63edacbefc64a6d45dddb12586b53bab4a2d40dc /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | b15fad9df4e813b22c6f538670ced462f62c7748 (diff) | |
| download | bcm5719-llvm-1352be2bd3249fcb0225ff41939973078756aff2.tar.gz bcm5719-llvm-1352be2bd3249fcb0225ff41939973078756aff2.zip | |
Move getCommonSubClass() into TRI.
It will soon need the context.
llvm-svn: 140896
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineRegisterInfo.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index d513f29e7c1..97d9d0f922c 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -18,7 +18,7 @@ using namespace llvm; MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) - : IsSSA(true) { + : TRI(&TRI), IsSSA(true) { VRegInfo.reserve(256); RegAllocHints.reserve(256); UsedPhysRegs.resize(TRI.getNumRegs()); @@ -54,7 +54,7 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg, const TargetRegisterClass *OldRC = getRegClass(Reg); if (OldRC == RC) return RC; - const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC); + const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); if (!NewRC || NewRC == OldRC) return NewRC; if (NewRC->getNumRegs() < MinNumRegs) @@ -66,7 +66,6 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg, bool MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { const TargetInstrInfo *TII = TM.getInstrInfo(); - const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterClass *OldRC = getRegClass(Reg); const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); @@ -86,7 +85,7 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { const TargetRegisterClass *OpRC = TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI); if (OpRC) - NewRC = getCommonSubClass(NewRC, OpRC); + NewRC = TRI->getCommonSubClass(NewRC, OpRC); if (!NewRC || NewRC == OldRC) return false; } |
