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* Partition use lists so defs always come before uses.Jakob Stoklund Olesen2012-08-091-3/+11
| | | | | | | | | | | | | | | | This makes it possible to speed up def_iterator by stopping at the first use. This makes def_empty() and getUniqueVRegDef() much faster when there are many uses. In a +Asserts build, LiveVariables is 100x faster in one case because getVRegDef() has an assertion that would scan to the end of a def_iterator chain. Spill weight calculation is significantly faster (300x in one case) because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP) which calls def_empty(%RIP). llvm-svn: 161634
* Don't use pointer-pointers for the register use lists.Jakob Stoklund Olesen2012-08-091-45/+39
| | | | | | | | | | | Use a more conventional doubly linked list where the Prev pointers form a cycle. This means it is no longer necessary to adjust the Prev pointers when reallocating the VRegInfo array. The test changes are required because the register allocation hint is using the use-list order to break ties. llvm-svn: 161633
* Move use list management into MachineRegisterInfo.Jakob Stoklund Olesen2012-08-091-0/+37
| | | | | | | | | | | | | | Register MachineOperands are kept in linked lists accessible via MRI's reg_iterator interfaces. The linked list management was handled partly by MachineOperand methods, partly by MRI methods. Move all of the list management into MRI, delete MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo(). Be more explicit about handling the cases where an MRI pointer isn't available. llvm-svn: 161632
* Inline MachineRegisterInfo::hasOneUseAndrew Trick2012-07-301-7/+0
| | | | llvm-svn: 161007
* Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren2012-07-021-0/+2
| | | | | | | register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. llvm-svn: 159545
* Add getUniqueVRegDef to MachineRegisterInfo.Manman Ren2012-06-291-0/+11
| | | | | | This comes in handy during peephole optimization. llvm-svn: 159453
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-4/+4
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. llvm-svn: 153511
* Microoptimize getVRegDef. def_begin isn't free, don't compute it twice.Benjamin Kramer2012-03-101-3/+2
| | | | llvm-svn: 152492
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-211-3/+11
| | | | | | | | | | | | | Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. llvm-svn: 151032
* Transfer regmasks to MRI.Jakob Stoklund Olesen2012-02-171-10/+2
| | | | | | | | | MRI keeps track of which physregs have been used. Make sure it gets updated with all the regmask-clobbered registers. Delete the closePhysRegsUsed() function which isn't necessary. llvm-svn: 150830
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-161-0/+18
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-051-0/+4
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Handle sub-register operands in recomputeRegClass().Jakob Stoklund Olesen2011-12-191-4/+6
| | | | | | | | | | | Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. llvm-svn: 146874
* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-121-4/+1
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. llvm-svn: 141836
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-4/+3
| | | | | | It will soon need the context. llvm-svn: 140896
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-221-4/+6
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. llvm-svn: 140339
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-091-1/+32
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. llvm-svn: 137123
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-291-1/+2
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. llvm-svn: 136532
* Remove RegClass2VRegMap from MachineRegisterInfo.Evan Cheng2011-06-271-14/+0
| | | | llvm-svn: 133967
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-8/+1
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-1/+8
| | | | llvm-svn: 124611
* Use IndexedMap for MachineRegisterInfo as well. No functional change.Jakob Stoklund Olesen2011-01-091-19/+22
| | | | llvm-svn: 123106
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-061-0/+14
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. llvm-svn: 115875
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-101-6/+3
| | | | llvm-svn: 108062
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-241-14/+25
| | | | | | and to clean up unused incoming physregs from the live-in list. llvm-svn: 106805
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
| | | | | | std::vector. llvm-svn: 106298
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Remove unused function.Benjamin Kramer2010-05-291-69/+0
| | | | llvm-svn: 105100
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-291-30/+12
| | | | llvm-svn: 105095
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-241-0/+9
| | | | llvm-svn: 104560
* Add a utility function for conservatively clearing kill flags, and makeDan Gohman2010-05-131-0/+9
| | | | | | use of it in MachineCSE. llvm-svn: 103726
* Silence warningJakob Stoklund Olesen2010-05-111-1/+1
| | | | llvm-svn: 103508
* Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen2010-05-111-0/+9
| | | | | | | | closure after allocating all blocks. Add a few more test cases for -regalloc=fast. llvm-svn: 103500
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng2010-04-281-28/+9
| | | | | | instructions for function arguments early and insert them after instruction selection is done. llvm-svn: 102554
* Insert dbg_value instructions for function entry block liveins (i.e. ↵Evan Cheng2010-04-261-1/+30
| | | | | | function arguments). llvm-svn: 102368
* Move the code for initialing the entry block livein set out ofDan Gohman2010-04-141-0/+5
| | | | | | SelectionDAGISel. llvm-svn: 101258
* Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman2010-04-141-0/+106
| | | | llvm-svn: 101254
* Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman2010-04-131-0/+14
| | | | llvm-svn: 101145
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-031-0/+13
| | | | llvm-svn: 97663
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-5/+3
| | | | llvm-svn: 82812
* Part 1.Evan Cheng2009-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-0/+2
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
| | | | llvm-svn: 69126
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-081-0/+18
| | | | llvm-svn: 60684
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
| | | | llvm-svn: 57844
* Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman2008-07-071-0/+3
| | | | | | their cleanup code. llvm-svn: 53194
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