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path: root/src/import/chips/p9/procedures/hwp/perv
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* dcc skew adjust procedure updateAnusha Reddy Rangareddygari2017-07-121-229/+248
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-07-121-45/+90
* p9_sbe_chiplet_reset updatesAnusha Reddy Rangareddygari2017-07-121-0/+2
* p9_{mem,sbe_chiplet}_pll_setup: Level 3Joachim Fenkes2017-07-112-3/+3
* p9_sbe_select_ex -- add option to skip HB checksJoe McGill2017-07-112-4/+12
* Restore backward compatibilty of SBE image with HB/HWSVSachin Gupta2017-07-071-0/+24
* Update p9_sbe_chiplet_reset to support MV GSD2PIBAbhishek Agarwal2017-07-031-0/+2
* p9_sbe_select_ex -- skip new checks for b_single=falseJoe McGill2017-07-031-2/+2
* p9_sbe_select_ex: add fused core booting supportGreg Still2017-07-031-31/+85
* p9_tp_stopclocks: Don't raise CFAM FENCE2 to keep PERV chiplet accessibleJoachim Fenkes2017-06-231-1/+1
* p9_sbe_tp_chiplet_init1: Set TP_TCPERV_SRAM_ENABLE_DCJoe Dery2017-06-231-0/+5
* Propagate "fused_core" IPL option into PU chipJoachim Fenkes2017-06-232-2/+16
* add support for OBUS PLL bucketsJoe McGill2017-06-232-14/+131
* p9_fastarray: Level 3Joachim Fenkes2017-06-192-8/+4
* p9_sbe_tracearray: Level 3Joachim Fenkes2017-06-192-36/+33
* p9_common_stopclocks: Level 3Joachim Fenkes2017-06-192-4/+16
* Check Scratch Register 3 bit 7 and set new ATTR_SECURE_SETTINGSMike Baiocchi2017-06-071-4/+15
* Added traces to figure out the infinite loop in the mpipl pathRaja Das2017-06-051-3/+6
* p9_fastarray: Fix ABIST engines not running to completionJoachim Fenkes2017-06-021-4/+4
* p9_fastarray: Raise CTRL_CC_SDIS_DC_N during dumpJoachim Fenkes2017-06-022-0/+8
* p9_sbe_tp_switch_gears, p9_sbe_gear_switcher: Level 3Joachim Fenkes2017-06-014-9/+14
* p9_sbe_common: Level 3Joachim Fenkes2017-06-012-21/+48
* Stopclocks procedure to stop PLL region alsoSoma BhanuTej2017-05-312-9/+8
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-05-311-5/+5
* Check scrach register 3 bit 6 before potentially disabling securityNick Bofferding2017-05-291-6/+16
* p9_perv_sbe_cmn: Level 3Joachim Fenkes2017-05-272-4/+4
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-271-0/+23
* p9_sbe_nest_initf -- add HWP support to scan n3_br_fureJoe McGill2017-05-191-0/+11
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-111-16/+141
* p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34sJoachim Fenkes2017-05-042-4/+2
* Initf proc updatesAnusha Reddy Rangareddygari2017-04-284-161/+471
* using literal definitionsSoma BhanuTej2017-04-192-61/+57
* p9_sbe_startclock_chiplets updatesAnusha Reddy Rangareddygari2017-04-191-0/+21
* Do the real LPC reset for DD2CHRISTINA L. GRAVES2017-04-062-1/+33
* literal definitionsAnusha Reddy Rangareddygari2017-04-064-62/+65
* IPL: Change select_ex to use core/eq targets instead of pervYue Du2017-03-311-25/+23
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-312-0/+38
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-292-4/+65
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-03-231-3/+5
* p9_sbe_tp_chiplet_init3: Start PLL SL clocksJoachim Fenkes2017-03-231-2/+12
* Inclusion of p9_ring_id.hKahn Evans2017-03-219-9/+18
* Update proc_select_ex to remove target from old MC groupcrgeddes2017-03-211-93/+72
* p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2017-03-141-1/+9
* tp/nest reset: add INEX scan type in non-gptr/time/repr scan0 operationJoe Dery2017-03-142-2/+2
* Adding cfam fences to p9_tp_stopclocksSoma BhanuTej2017-03-142-5/+23
* stopclocks: Don't set ABSTCLK_MUXSEL on clock stopJoachim Fenkes2017-03-141-3/+1
* Meshctrl setup updateAnusha Reddy Rangareddygari2017-03-101-51/+154
* p9_fastarray: Fix hang, add timeoutJoachim Fenkes2017-03-072-6/+31
* p9_fastarray: Fix scanning after dump, make dump repeatableJoachim Fenkes2017-02-281-6/+21
* Defer setup of MC multicast groups in async modeDean Sanner2017-02-242-1/+12
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