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authorLokesh Vutla <lokeshvutla@ti.com>2016-05-23 13:31:19 +0530
committerTom Rini <trini@konsulko.com>2016-05-27 15:47:57 -0400
commit9b77b19178446393fce2e74554815c17454f8da8 (patch)
tree72bf8dd28d739040e0829f59617dad0a6149c127 /arch/arm/cpu/armv7
parent87c2f76f3fae11bf559996505e23b37d03f4c5dc (diff)
downloadtalos-obmc-uboot-9b77b19178446393fce2e74554815c17454f8da8.tar.gz
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ARM: OMAP4+: Fix DPLL programming sequence
All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index ef2ac98217..2de9935765 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
+
+ bypass_dpll(base);
goto setup_post_dividers;
}
}
@@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
writel(temp, &dpll_regs->cm_clksel_dpll);
+setup_post_dividers:
+ setup_post_dividers(base, params);
+
/* Lock */
if (lock)
do_lock_dpll(base);
-setup_post_dividers:
- setup_post_dividers(base, params);
-
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
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