| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added WR VREF register API and reset procedures | Stephen Glancy | 2016-09-26 | 4 | -1/+1105 |
| * | Added mss_pair.H to fix HB CI compile | Stephen Glancy | 2016-09-25 | 1 | -0/+35 |
| * | Change WR_CNTR_FW values | Brian Silver | 2016-09-25 | 4 | -21/+73 |
| * | adjust DEFAULT_POLL_LIMIT for VBU mc model | Joe McGill | 2016-09-25 | 1 | -1/+1 |
| * | Change the polling in memdiags so it's for sim only | Brian Silver | 2016-09-25 | 1 | -2/+9 |
| * | Header file updates based on 9067 figtree | Ben Gass | 2016-09-24 | 3 | -7/+4 |
| * | Add LRDIMM decoder and unit tests | Andre Marin | 2016-09-21 | 7 | -52/+2887 |
| * | Add enforcement of DDR4 DRAM on Nimbus via plug rules | Brian Silver | 2016-09-21 | 2 | -3/+18 |
| * | Change VPD to better account for deconfigured chiplets | Brian Silver | 2016-09-20 | 7 | -151/+280 |
| * | Add register API for PHY Rank Pair registers | Louis Stermole | 2016-09-20 | 8 | -18/+642 |
| * | Changes related to PHY register review, Round 3 | Louis Stermole | 2016-09-20 | 4 | -2/+41 |
| * | Remove EKB's unit test files | crgeddes | 2016-09-16 | 2 | -1406/+0 |
| * | Modify fake SPD API to take into account spd type | Andre Marin | 2016-09-16 | 3 | -44/+181 |
| * | Cleaned up memory_mrw_attributes.xml | Jacob Harvey | 2016-09-16 | 1 | -13/+68 |
| * | Fixed PHY impedance bugs and commments | Stephen Glancy | 2016-09-15 | 2 | -12/+12 |
| * | Fixed no DIMM configuration bug in xlate code | Stephen Glancy | 2016-09-15 | 1 | -1/+10 |
| * | Add bit field of master ranks attribute for PRD | Brian Silver | 2016-09-15 | 2 | -1/+106 |
| * | Change RCD, MRS polling delays; calculated no longer static | Brian Silver | 2016-09-14 | 2 | -0/+10 |
| * | Add SEQ timing parameters, DP16 RD Diag config 5 inits | Brian Silver | 2016-09-14 | 6 | -2/+128 |
| * | Fix dp16 workaround to return success if not ports were harmed | Brian Silver | 2016-09-13 | 1 | -0/+3 |
| * | Update memory library for 1R 4gbx4 DIMM | Brian Silver | 2016-09-13 | 5 | -171/+437 |
| * | Change SEQ timings, SEQ ODT, WC config and DQS polarity | Brian Silver | 2016-09-12 | 10 | -100/+661 |
| * | Add VPD decode and attributes for DQ and CKE maps | Brian Silver | 2016-09-12 | 6 | -3/+420 |
| * | Change DDR4 latency switch to always use MR0 A12 | Brian Silver | 2016-09-08 | 1 | -2/+3 |
| * | Change PHY to use GPO, RLO, WLO from VPD | Brian Silver | 2016-09-08 | 16 | -655/+475 |
| * | Migrate dimm module decoder from rdimm to common dir | Andre Marin | 2016-09-06 | 3 | -577/+593 |
| * | Add empty files for PHY SEQ, workarounds for mirroring | Brian Silver | 2016-09-06 | 4 | -0/+96 |
| * | Add phy_cntrl.C empty for mirroring | Brian Silver | 2016-09-06 | 1 | -0/+24 |
| * | Changes related to PHY register review | Brian Silver | 2016-09-03 | 9 | -568/+278 |
| * | Add SPD decoder fall back options for unsupported revisions | Andre Marin | 2016-09-02 | 1 | -8/+11 |
| * | Add empty base and lrdimm decoder file for HB CI mirroring | Andre Marin | 2016-09-02 | 5 | -0/+170 |
| * | Change VPD for power on and VBU | Grover Monster | 2016-09-02 | 6 | -251/+579 |
| * | Add ZQCL instruction after MRS have completed | Brian Silver | 2016-09-02 | 1 | -2/+42 |
| * | Create MRS data structures | Brian Silver | 2016-09-02 | 1 | -49/+9 |
| * | Modifying ATTRs for memory power thermal | Jacob Harvey | 2016-09-01 | 2 | -119/+310 |
| * | Add RCD infrastructure, remove RCD hardcodes from eff_config | Andre Marin | 2016-09-01 | 13 | -535/+921 |
| * | Avoid nullptr in vpd decode for ports with no DIMM | Brian Silver | 2016-08-31 | 1 | -9/+3 |
| * | Implement MRW attributes; dram_clks, db_util, 2n_mode | Brian Silver | 2016-08-30 | 3 | -186/+11 |
| * | Fix eff_config, remove custom_dimm | Jacob Harvey | 2016-08-30 | 16 | -568/+466 |
| * | Change freq system's sync to account for single MCBIST configs | Brian Silver | 2016-08-30 | 1 | -0/+10 |
| * | Add rudimentary memory plug rules | Brian Silver | 2016-08-26 | 7 | -14/+498 |
| * | Change DRAM output impedance value to be from MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS | Louis Stermole | 2016-08-25 | 5 | -47/+12 |
| * | Remove eff_config hardcoded values, mirroring, trfc_dlr, & modify ut's | Andre Marin | 2016-08-25 | 7 | -29/+99 |
| * | FAPI2 - Enable register ffdc support | Richard J. Knight | 2016-08-25 | 1 | -1/+1 |
| * | Change force_mclk_low to not bother in cycle sim | Brian Silver | 2016-08-24 | 2 | -38/+28 |
| * | Add informational error log for PHY during training | Brian Silver | 2016-08-24 | 1 | -1/+14 |
| * | Add f/w implementation of PHY duty cycle distortion cal | Brian Silver | 2016-08-24 | 3 | -2/+314 |
| * | Add ZQCL instruction after MRS have completed | Brian Silver | 2016-08-24 | 3 | -28/+113 |
| * | Add empty files for plug-rules mirror | Brian Silver | 2016-08-24 | 3 | -0/+72 |
| * | Added support for PHY drive strength attributes | Stephen Glancy | 2016-08-23 | 6 | -11/+1033 |
