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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-08-03 15:49:44 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-30 21:55:45 -0400 |
| commit | 54bc88b4d29d0d0d288aaccf79b8d4220848187b (patch) | |
| tree | 605d5c61bc22e00bb6df7da1e3d05d56caf1b24a /src/import/chips/p9/procedures/hwp/memory | |
| parent | e436c6b446ac80fdf050539edc746e0082219b86 (diff) | |
| download | talos-hostboot-54bc88b4d29d0d0d288aaccf79b8d4220848187b.tar.gz talos-hostboot-54bc88b4d29d0d0d288aaccf79b8d4220848187b.zip | |
Fix eff_config, remove custom_dimm
Change-Id: Icc9bf700cbdf41467c4b0733f878d98b5dd76fed
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27930
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28184
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
16 files changed, 466 insertions, 568 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index ec0d77f72..71a51e7bb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -53,16 +53,17 @@ namespace ddr4 /// @brief mrs0_data ctor /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// @note Burst Length will always be set to fixed x8 (0) +/// @note Burst Chop (x4) is not supported /// mrs00_data::mrs00_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): iv_burst_length(0), - iv_read_burst_type(0), + iv_read_burst_type(fapi2::ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL), iv_dll_reset(fapi2::ENUM_ATTR_EFF_DRAM_DLL_RESET_NO), - iv_test_mode(0), + iv_test_mode(fapi2::ENUM_ATTR_EFF_DRAM_TM_NORMAL), iv_write_recovery(0), iv_cas_latency(0) { - FAPI_TRY( mss::eff_dram_bl(i_target, iv_burst_length) ); FAPI_TRY( mss::eff_dram_rbt(i_target, iv_read_burst_type) ); FAPI_TRY( mss::eff_dram_cl(i_target, iv_cas_latency) ); FAPI_TRY( mss::eff_dram_dll_reset(i_target, iv_dll_reset) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index 01f6cf413..4b54b457e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -55,16 +55,16 @@ namespace ddr4 /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// mrs04_data::mrs04_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): - iv_max_pd_mode(0), - iv_temp_refresh_range(0), - iv_temp_ref_mode(0), - iv_vref_mon(0), - iv_cs_cmd_latency(0), - iv_ref_abort(0), + iv_max_pd_mode(fapi2::ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE), + iv_temp_refresh_range(fapi2::ENUM_ATTR_MSS_MRW_TEMP_REFRESH_RANGE_NORMAL), + iv_temp_ref_mode(fapi2::ENUM_ATTR_EFF_TEMP_REFRESH_MODE_DISABLE), + iv_vref_mon(fapi2::ENUM_ATTR_EFF_INTERNAL_VREF_MONITOR_DISABLE), + iv_cs_cmd_latency(fapi2::ENUM_ATTR_EFF_CS_CMD_LATENCY_DISABLE), + iv_ref_abort(fapi2::ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE), iv_rd_pre_train_mode(fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE), - iv_rd_preamble(0), - iv_wr_preamble(0), - iv_ppr(0) + iv_rd_preamble(fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE), + iv_wr_preamble(fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK), + iv_ppr(fapi2::ENUM_ATTR_EFF_DRAM_PPR_NOT_SUPPORTED) { FAPI_TRY( mss::eff_max_powerdown_mode(i_target, iv_max_pd_mode) ); FAPI_TRY( mss::mrw_temp_refresh_range(iv_temp_refresh_range) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 74acd2116..a6a0204f8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -55,14 +55,14 @@ namespace ddr4 /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// mrs05_data::mrs05_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): - iv_ca_parity_latency(0), - iv_crc_error_clear(0), - iv_ca_parity_error_status(0), - iv_odt_input_buffer(fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED), - iv_ca_parity(0), - iv_data_mask(0), - iv_write_dbi(0), - iv_read_dbi(0) + iv_ca_parity_latency(fapi2::ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE), + iv_crc_error_clear(fapi2::ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR), + iv_ca_parity_error_status(fapi2::ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR), + iv_odt_input_buffer(fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED), + iv_ca_parity(fapi2::ENUM_ATTR_EFF_CA_PARITY_DISABLE), + iv_data_mask(fapi2::ENUM_ATTR_EFF_DATA_MASK_DISABLE), + iv_write_dbi(fapi2::ENUM_ATTR_EFF_WRITE_DBI_DISABLE), + iv_read_dbi(fapi2::ENUM_ATTR_EFF_READ_DBI_DISABLE) { FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency) ); FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index 082c9f36b..aeb3f1a29 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -35,6 +35,7 @@ // fapi2 #include <fapi2.H> #include <vpd_access.H> +#include <utility> // mss lib #include <lib/eff_config/eff_config.H> @@ -44,6 +45,7 @@ #include <lib/eff_config/timing.H> #include <lib/dimm/rank.H> #include <lib/utils/conversions.H> +#include <lib/utils/find.H> #include <lib/utils/fake_vpd.H> using fapi2::TARGET_TYPE_MCA; @@ -109,6 +111,7 @@ static uint64_t ibt_helper(const uint8_t i_ibt) fapi2::ReturnCode eff_config::dram_gen(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data ) { + //TODO: RTC 159777: Change eff_config class to use iv's for mcs, port and dimm position const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); const auto l_dimm_num = index(i_target); @@ -321,7 +324,7 @@ fapi2::ReturnCode eff_config::dimm_size(const fapi2::Target<TARGET_TYPE_DIMM>& i uint32_t l_attrs_dimm_size[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_size(l_mcs, &l_attrs_dimm_size[0][0]) ); - l_attrs_dimm_size[l_port_num][l_dimm_num] = uint8_t(l_dimm_size); + l_attrs_dimm_size[l_port_num][l_dimm_num] = l_dimm_size; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_SIZE, l_mcs, l_attrs_dimm_size) ); } @@ -363,7 +366,7 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T { uint8_t l_temp_refresh_range = 0; uint8_t l_refresh_mode = 0; - uint64_t l_trefi_in_ps = 0; + int64_t l_trefi_in_ps = 0; FAPI_TRY( mss::mrw_temp_refresh_range(l_temp_refresh_range), "Failed mrw_temp_refresh_range()" ); FAPI_TRY( mss::mrw_fine_refresh_mode(l_refresh_mode), "Failed mrw_fine_refresh_mode()" ); @@ -376,7 +379,7 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T FAPI_TRY( calc_trefi( mss::refresh_rate::REF1X, l_temp_refresh_range, l_trefi_in_ps), - "Failed to calculate tREF1" ); + "Failed to calculate tREF1 in refresh_interval_time for target %s", mss::c_str(i_target) ); break; case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X: @@ -385,7 +388,7 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T FAPI_TRY( calc_trefi( mss::refresh_rate::REF2X, l_temp_refresh_range, l_trefi_in_ps), - "Failed to calculate tREF2" ); + "Failed to calculate tREF2 for target %s", mss::c_str(i_target) ); break; case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X: @@ -394,7 +397,7 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T FAPI_TRY( calc_trefi( mss::refresh_rate::REF4X, l_temp_refresh_range, l_trefi_in_ps), - "Failed to calculate tREF4" ); + "Failed to calculate tREF4 for target %s", mss::c_str(i_target) ); break; default: @@ -411,36 +414,31 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T } { - // Calculate clock period (tCK) from selected freq from mss_freq - uint64_t l_tCK_in_ps = 0; - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calclate clock period"); - - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + // Calculate refresh cycle time in nCK & set attribute + const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); + const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); - { - // Calculate refresh cycle time in nCK & set attribute - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); + std::vector<uint16_t> l_mcs_attrs_trefi(PORTS_PER_MCS, 0); + uint16_t l_trefi_in_nck = 0; - std::vector<uint16_t> l_mcs_attrs_trefi(PORTS_PER_MCS, 0); - uint16_t l_trefi_in_nck ; + // Retrieve MCS attribute data + FAPI_TRY( eff_dram_trefi(l_mcs, l_mcs_attrs_trefi.data()) ); - // Retrieve MCS attribute data - FAPI_TRY( eff_dram_trefi(l_mcs, l_mcs_attrs_trefi.data()) ); + // Calculate nck + // iv_tCK-in_ps will always be positive + FAPI_TRY( calc_nck(l_trefi_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trefi_in_nck), + "Error in calculating tREFI for target %s, with value of l_trefi_in_ps: %d", mss::c_str(i_target), l_trefi_in_ps); - // Calculate nck - l_trefi_in_nck = calc_nck(l_trefi_in_ps, l_tCK_in_ps, uint64_t(INVERSE_DDR4_CORRECTION_FACTOR)); - FAPI_INF("Calculated tREFI (ps): %d, tREFI (nck): %d", l_trefi_in_ps, l_trefi_in_ps); + FAPI_INF("Calculated tREFI (ps): %d, tREFI (nck): %d", l_trefi_in_ps, l_trefi_in_nck); - // Update MCS attribute - l_mcs_attrs_trefi[l_port_num] = l_trefi_in_nck; + // Update MCS attribute + l_mcs_attrs_trefi[l_port_num] = l_trefi_in_nck; - // casts vector into the type FAPI_ATTR_SET is expecting by deduction - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TREFI, - l_mcs, - UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trefi, PORTS_PER_MCS)), - "Failed to set tREFI attribute"); - } + // casts vector into the type FAPI_ATTR_SET is expecting by deduction + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TREFI, + l_mcs, + UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trefi, PORTS_PER_MCS)), + "Failed to set tREFI attribute"); } fapi_try_exit: @@ -510,38 +508,30 @@ fapi2::ReturnCode eff_config::refresh_cycle_time(const fapi2::Target<TARGET_TYPE } { - // Calculate clock period (tCK) from selected freq from mss_freq - int64_t l_tCK_in_ps = 0; - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), - "Failed to calculate clock period (tCK)"); - - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); - - { - // Calculate refresh cycle time in nCK & set attribute - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); + // Calculate refresh cycle time in nCK & set attribute + const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); + const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); - uint16_t l_trfc_in_nck = 0; - std::vector<uint16_t> l_mcs_attrs_trfc(PORTS_PER_MCS, 0); + uint16_t l_trfc_in_nck = 0; + std::vector<uint16_t> l_mcs_attrs_trfc(PORTS_PER_MCS, 0); - // Retrieve MCS attribute data - FAPI_TRY( eff_dram_trfc(l_mcs, l_mcs_attrs_trfc.data()), - "Failed to retrieve tRFC attribute" ); + // Retrieve MCS attribute data + FAPI_TRY( eff_dram_trfc(l_mcs, l_mcs_attrs_trfc.data()), + "Failed to retrieve tRFC attribute" ); - // Calculate nck - l_trfc_in_nck = calc_nck(l_trfc_in_ps, l_tCK_in_ps, int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); - FAPI_INF("Calculated tRFC (ps): %d, tRFC (nck): %d", l_trfc_in_ps, l_trfc_in_nck); + // Calculate nck + FAPI_TRY( calc_nck(l_trfc_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_in_nck), + "Error in calculating l_tRFC for target %s, with value of l_trfc_in_ps: %d", mss::c_str(i_target), l_trfc_in_ps); + FAPI_INF("Calculated tRFC (ps): %d, tRFC (nck): %d", l_trfc_in_ps, l_trfc_in_nck); - // Update MCS attribute - l_mcs_attrs_trfc[l_port_num] = l_trfc_in_nck; + // Update MCS attribute + l_mcs_attrs_trfc[l_port_num] = l_trfc_in_nck; - // casts vector into the type FAPI_ATTR_SET is expecting by deduction - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC, - l_mcs, - UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc, PORTS_PER_MCS) ), - "Failed to set tRFC attribute" ); - } + // casts vector into the type FAPI_ATTR_SET is expecting by deduction + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC, + l_mcs, + UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc, PORTS_PER_MCS) ), + "Failed to set tRFC attribute" ); } fapi_try_exit: @@ -579,7 +569,7 @@ fapi2::ReturnCode eff_config::refresh_cycle_time_dlr(const fapi2::Target<TARGET_ FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); // Calculate refresh cycle time in nck - l_trfc_dlr_in_nck = calc_nck(l_trfc_dlr_in_ps, l_tCK_in_ps, uint64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_trfc_dlr_in_ps, l_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_dlr_in_nck)); FAPI_INF("Calculated clock period (tCK): %d, tRFC_DLR (ps): %d, tRFC_DLR (nck): %d", l_tCK_in_ps, l_trfc_dlr_in_ps, l_trfc_dlr_in_nck); @@ -678,40 +668,15 @@ fapi_try_exit: } /// -/// @brief Determines & sets effective config for custom dimm -/// @param[in] i_target FAPI2 target -/// @return fapi2::FAPI2_RC_SUCCESS if okay -/// -fapi2::ReturnCode eff_config::custom_dimm(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) -{ - // TK - RIT skeleton. Need to finish - AAM - // Targets - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); - - // Current index - const auto l_port_num = index(l_mca); - const auto l_dimm_num = index(i_target); - - uint8_t l_attrs_custom_dimm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; - FAPI_TRY(eff_custom_dimm(l_mcs, &l_attrs_custom_dimm[0][0])); - - l_attrs_custom_dimm[l_port_num][l_dimm_num] = 0x00; - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CUSTOM_DIMM, l_mcs, l_attrs_custom_dimm) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Determines & sets effective config for tDQS /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note Sets TDQS to off for x4, sets to on for x8 /// fapi2::ReturnCode eff_config::dram_dqs_time(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM uint8_t l_attrs_dqs_time[PORTS_PER_MCS] = {}; + uint8_t l_dram_width = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); @@ -720,8 +685,17 @@ fapi2::ReturnCode eff_config::dram_dqs_time(const fapi2::Target<TARGET_TYPE_DIMM // Current index const auto l_port_num = index(l_mca); + //Get the DRAM width + FAPI_TRY( iv_pDecoder->device_width(i_target, l_dram_width) ); + + // Get & update MCS attribute FAPI_TRY( eff_dram_tdqs(l_mcs, &l_attrs_dqs_time[0]) ); - l_attrs_dqs_time[l_port_num] = 0x01; + FAPI_INF("Dram width is %ld for target %s", l_dram_width, mss::c_str(i_target)); + + //Only possible dram width are x4, x8. If x8, tdqs is available, else not available + l_attrs_dqs_time[l_port_num] = (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ? + fapi2::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE : fapi2::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TDQS, l_mcs, l_attrs_dqs_time) ); fapi_try_exit: @@ -735,20 +709,52 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::dram_tccd_l(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM - uint8_t l_attrs_tccd_l[PORTS_PER_MCS] = {}; + int64_t l_tccd_mtb = 0; + int64_t l_tccd_ftb = 0; + int64_t l_tccd_in_ps = 0; - // Targets - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); + //Get the tCCD timing values + FAPI_TRY( iv_pDecoder->min_tccd_l(i_target, l_tccd_mtb), "failed to get min_tccd_l" ); + FAPI_TRY( iv_pDecoder->fine_offset_min_tccd_l(i_target, l_tccd_ftb) ); + + //Calculate tccd in ps + { + int64_t l_ftb = 0; + int64_t l_mtb = 0; + + FAPI_TRY( iv_pDecoder->medium_timebase(i_target, l_mtb) ); + FAPI_TRY( iv_pDecoder->fine_timebase(i_target, l_ftb) ); + + l_tccd_in_ps = calc_timing_from_timebase(l_tccd_mtb, l_mtb, l_tccd_ftb, l_ftb); + } - // Current index - const auto l_port_num = index(l_mca); - FAPI_TRY( eff_dram_tccd_l(l_mcs, &l_attrs_tccd_l[0]) ); + { + // Calculate refresh cycle time in nCK & set attribute + const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); + const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); - l_attrs_tccd_l[l_port_num] = 0x06; - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TCCD_L, l_mcs, l_attrs_tccd_l) ); + uint8_t l_tccd_in_nck = 0; + std::vector<uint8_t> l_mcs_attrs_tccd(PORTS_PER_MCS, 0); + + // Retrieve MCS attribute data + FAPI_TRY( eff_dram_tccd_l(l_mcs, l_mcs_attrs_tccd.data()), + "Failed to retrieve tCCD attribute" ); + + // Calculate nck + FAPI_TRY ( calc_nck(l_tccd_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_tccd_in_nck), + "Error in calculating tccd for target %s, with value of l_tccd_in_ps: %d", mss::c_str(i_target), l_tccd_in_ps); + FAPI_INF("Calculated tCCD (ps): %d, tCCD (nck): %d", l_tccd_in_ps, l_tccd_in_nck); + + // Update MCS attribute + l_mcs_attrs_tccd[l_port_num] = l_tccd_in_nck; + + // casts vector into the type FAPI_ATTR_SET is expecting by deduction + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TCCD_L, + l_mcs, + UINT8_VECTOR_TO_1D_ARRAY(l_mcs_attrs_tccd, PORTS_PER_MCS) ), + "Failed to set tCCD_L attribute" ); + } fapi_try_exit: return fapi2::current_err; @@ -1460,52 +1466,45 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::dram_twr(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM - std::vector<uint8_t> l_attrs_twr(PORTS_PER_MCS, 0); - - // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); - - // Current index - const auto l_port_num = index(l_mca); - - FAPI_TRY( eff_dram_twr(l_mcs, l_attrs_twr.data()) ); + const auto l_port_num = index(find_target<TARGET_TYPE_MCA>(i_target)); + int64_t l_twr_in_ps = 0; - l_attrs_twr[l_port_num] = 0x12; - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TWR, - l_mcs, - UINT8_VECTOR_TO_1D_ARRAY(l_attrs_twr, PORTS_PER_MCS)), - "Failed setting attribute for tWR"); -fapi_try_exit: - return fapi2::current_err; -} + // Calculate twr (in ps) + { + constexpr int64_t l_twr_ftb = 0; + int64_t l_twr_mtb = 0; + int64_t l_ftb = 0; + int64_t l_mtb = 0; -/// -/// @brief Determines & sets effective config for burst length (BL) -/// @param[in] i_target FAPI2 target -/// @return fapi2::FAPI2_RC_SUCCESS if okay -/// -fapi2::ReturnCode eff_config::burst_length(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) -{ - // TK - RIT skeleton. Need to finish - AAM - std::vector<uint8_t> l_attrs_bl(PORTS_PER_MCS, 0); + FAPI_TRY( iv_pDecoder->medium_timebase(i_target, l_mtb) ); + FAPI_TRY( iv_pDecoder->fine_timebase(i_target, l_ftb) ); + FAPI_TRY( iv_pDecoder->min_write_recovery_time(i_target, l_twr_mtb) ); + FAPI_INF("Values for write_recovery (twr) in MTB units: medium timebase: %ld, fine timebase: %ld, and min write: %ld", + l_mtb, l_ftb, l_twr_mtb); + l_twr_in_ps = calc_timing_from_timebase(l_twr_mtb, l_mtb, l_twr_ftb, l_ftb); + } - // Targets - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); + { + std::vector<uint8_t> l_attrs_dram_twr(PORTS_PER_MCS, 0); + uint8_t l_twr_in_nck = 0; - // Current index - const auto l_port_num = index(l_mca); + FAPI_INF("iv tck is %d", iv_tCK_in_ps); + // Calculate tNCK + FAPI_TRY( calc_nck(l_twr_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_twr_in_nck), + "Error in calculating l_twr_in_nck for target %s, with value of l_twr_in_ps: %d", mss::c_str(i_target), l_twr_in_ps); - FAPI_TRY( eff_dram_bl(l_mcs, l_attrs_bl.data()) ); + FAPI_INF("Calculated tWR (ps): %d, tWR (nck): %d for target: %s", l_twr_in_ps, l_twr_in_nck, mss::c_str(i_target)); - l_attrs_bl[l_port_num] = 0x00; + // Get & update MCS attribute + FAPI_TRY( eff_dram_twr(l_mcs, l_attrs_dram_twr.data()) ); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_BL, - l_mcs, - UINT8_VECTOR_TO_1D_ARRAY(l_attrs_bl, PORTS_PER_MCS)), - "Failed setting attribute for BL"); + l_attrs_dram_twr[l_port_num] = l_twr_in_nck; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TWR, + l_mcs, + UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_twr, PORTS_PER_MCS)), + "Failed setting attribute for DRAM_TWR"); + } fapi_try_exit: return fapi2::current_err; @@ -1518,7 +1517,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::read_burst_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM uint8_t l_attrs_rbt[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; // Targets @@ -1531,7 +1529,7 @@ fapi2::ReturnCode eff_config::read_burst_type(const fapi2::Target<TARGET_TYPE_DI FAPI_TRY( eff_dram_rbt(l_mcs, &l_attrs_rbt[0][0]) ); - l_attrs_rbt[l_port_num][l_dimm_num] = 0x00; + l_attrs_rbt[l_port_num][l_dimm_num] = fapi2::ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RBT, l_mcs, l_attrs_rbt), "Failed setting attribute for RTB"); @@ -1544,10 +1542,11 @@ fapi_try_exit: /// @brief Determines & sets effective config for TM /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note dram testing mode +/// @note always disabled /// fapi2::ReturnCode eff_config::dram_tm(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM uint8_t l_attrs_tm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; // Targets @@ -1560,7 +1559,7 @@ fapi2::ReturnCode eff_config::dram_tm(const fapi2::Target<TARGET_TYPE_DIMM>& i_t FAPI_TRY( eff_dram_tm(l_mcs, &l_attrs_tm[0][0]) ); - l_attrs_tm[l_port_num][l_dimm_num] = 0x00; + l_attrs_tm[l_port_num][l_dimm_num] = fapi2::ENUM_ATTR_EFF_DRAM_TM_NORMAL; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TM, l_mcs, l_attrs_tm), "Failed setting attribute for BL"); @@ -1574,22 +1573,82 @@ fapi_try_exit: /// @brief Determines & sets effective config for cwl /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note Sets CAS Write Latency, depending on frequency and ATTR_MSS_MT_PREAMBLE /// fapi2::ReturnCode eff_config::dram_cwl(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + + // Taken from DDR4 JEDEC spec 1716.78C + // Proposed DDR4 Full spec update(79-4A) + // Page 26, Table 7 + static std::pair<uint64_t, uint8_t> CWL_TABLE_1 [6] = + { + {1600, 9}, + {1866, 10}, + {2133, 11}, + {2400, 12}, + {2666, 14}, + {3200, 16}, + }; + static std::pair<uint64_t, uint8_t> CWL_TABLE_2 [3] = + { + {2400, 14}, + {2666, 16}, + {3200, 18}, + }; + std::vector<uint8_t> l_attrs_cwl(PORTS_PER_MCS, 0); + uint8_t l_cwl = 0; + uint64_t l_freq; + uint8_t l_preamble = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); - + const auto l_mcbist = find_target <TARGET_TYPE_MCBIST>(i_target); // Current index const auto l_port_num = index(l_mca); + + FAPI_TRY (vpd_mt_preamble (l_mca, l_preamble) ); + + //get the first nibble as according to vpd. 4-7 is read, 0-3 for write + l_preamble = l_preamble & 0x0F; + + FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), + fapi2::MSS_INVALID_VPD_MT_PREAMBLE() + .set_VALUE(l_preamble) + .set_DIMM_TARGET(i_target), + "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", + c_str(i_target), + l_preamble ); + + FAPI_TRY( mss::freq(l_mcbist, l_freq) ); + + // Using an if branch because a ternary conditional wasn't working with params for find_value_from_key + if (l_preamble == 0) + { + FAPI_TRY( mss::find_value_from_key( CWL_TABLE_1, + l_freq, l_cwl), + "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d", + l_freq, + l_preamble); + } + else + { + FAPI_TRY( mss::find_value_from_key( CWL_TABLE_2, + l_freq, l_cwl), + "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d", + l_freq, + l_preamble); + + } + FAPI_TRY( eff_dram_cwl(l_mcs, l_attrs_cwl.data()) ); + l_attrs_cwl[l_port_num] = l_cwl; + + FAPI_INF("Calculated CAS Write Latency is %d", l_cwl); - l_attrs_cwl[l_port_num] = 0x0C; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_CWL, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_cwl, PORTS_PER_MCS)), @@ -1603,10 +1662,11 @@ fapi_try_exit: /// @brief Determines & sets effective config for lpasr /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note from JEDEC DDR4 DRAM MR2 page 26 +/// @note All DDR4 supports auto refresh, setting to default /// fapi2::ReturnCode eff_config::dram_lpasr(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_lpasr(PORTS_PER_MCS, 0); // Targets @@ -1618,7 +1678,8 @@ fapi2::ReturnCode eff_config::dram_lpasr(const fapi2::Target<TARGET_TYPE_DIMM>& FAPI_TRY( eff_dram_lpasr(l_mcs, l_attrs_lpasr.data()) ); - l_attrs_lpasr[l_port_num] = 0x00; + l_attrs_lpasr[l_port_num] = fapi2::ENUM_ATTR_EFF_DRAM_LPASR_ASR; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_LPASR, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_lpasr, PORTS_PER_MCS)), @@ -1635,7 +1696,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::additive_latency(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_dram_al(PORTS_PER_MCS, 0); // Targets @@ -1647,7 +1707,7 @@ fapi2::ReturnCode eff_config::additive_latency(const fapi2::Target<TARGET_TYPE_D FAPI_TRY( eff_dram_al(l_mcs, l_attrs_dram_al.data()) ); - l_attrs_dram_al[l_port_num] = 0x00; + l_attrs_dram_al[l_port_num] = fapi2::ENUM_ATTR_EFF_DRAM_AL_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_AL, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_al, PORTS_PER_MCS)), @@ -1722,7 +1782,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::write_level_enable(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_wr_lvl_enable(PORTS_PER_MCS, 0); // Targets @@ -1734,7 +1793,7 @@ fapi2::ReturnCode eff_config::write_level_enable(const fapi2::Target<TARGET_TYPE FAPI_TRY( eff_dram_wr_lvl_enable(l_mcs, l_attrs_wr_lvl_enable.data()) ); - l_attrs_wr_lvl_enable[l_port_num] = 0x00; + l_attrs_wr_lvl_enable[l_port_num] = fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_WR_LVL_ENABLE, l_mcs, @@ -1751,7 +1810,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::output_buffer(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_output_buffer(PORTS_PER_MCS, 0); // Targets @@ -1763,7 +1821,7 @@ fapi2::ReturnCode eff_config::output_buffer(const fapi2::Target<TARGET_TYPE_DIMM FAPI_TRY( eff_dram_output_buffer(l_mcs, l_attrs_output_buffer.data()) ); - l_attrs_output_buffer[l_port_num] = 0x00; + l_attrs_output_buffer[l_port_num] = fapi2::ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_OUTPUT_BUFFER, l_mcs, @@ -1901,7 +1959,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::ca_parity_latency(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //TODO: RTC 159554 Update RAS related attributes std::vector<uint8_t> l_attrs_ca_parity_latency(PORTS_PER_MCS, 0); // Targets @@ -1912,9 +1970,7 @@ fapi2::ReturnCode eff_config::ca_parity_latency(const fapi2::Target<TARGET_TYPE_ const auto l_port_num = index(l_mca); FAPI_TRY( eff_ca_parity_latency(l_mcs, l_attrs_ca_parity_latency.data()) ); - - l_attrs_ca_parity_latency[l_port_num] = 0x00; - + l_attrs_ca_parity_latency[l_port_num] = fapi2::ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CA_PARITY_LATENCY, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_ca_parity_latency, PORTS_PER_MCS)), @@ -1930,7 +1986,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::crc_error_clear(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //TODO: RTC 159554 Update RAS related attributes std::vector<uint8_t> l_attrs_crc_error_clear(PORTS_PER_MCS, 0); // Targets @@ -1942,7 +1998,7 @@ fapi2::ReturnCode eff_config::crc_error_clear(const fapi2::Target<TARGET_TYPE_DI FAPI_TRY( eff_crc_error_clear(l_mcs, l_attrs_crc_error_clear.data()) ); - l_attrs_crc_error_clear[l_port_num] = 0x01; + l_attrs_crc_error_clear[l_port_num] = fapi2::ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CRC_ERROR_CLEAR, l_mcs, @@ -1959,7 +2015,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::ca_parity_error_status(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //TODO: RTC 159554 Update RAS related attributes std::vector<uint8_t> l_attrs_ca_parity_error_status(PORTS_PER_MCS, 0); // Targets @@ -1971,7 +2027,7 @@ fapi2::ReturnCode eff_config::ca_parity_error_status(const fapi2::Target<TARGET_ FAPI_TRY( eff_ca_parity_error_status(l_mcs, l_attrs_ca_parity_error_status.data()) ); - l_attrs_ca_parity_error_status[l_port_num] = 0x01; + l_attrs_ca_parity_error_status[l_port_num] = fapi2::ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CA_PARITY_ERROR_STATUS, l_mcs, @@ -1988,7 +2044,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::ca_parity(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //TODO: RTC 159554 Update RAS related attributes std::vector<uint8_t> l_attrs_ca_parity(PORTS_PER_MCS, 0); // Targets @@ -2000,7 +2056,7 @@ fapi2::ReturnCode eff_config::ca_parity(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( eff_ca_parity(l_mcs, l_attrs_ca_parity.data()) ); - l_attrs_ca_parity[l_port_num] = 0x00; + l_attrs_ca_parity[l_port_num] = fapi2::ENUM_ATTR_EFF_CA_PARITY_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CA_PARITY, l_mcs, @@ -2050,10 +2106,11 @@ fapi_try_exit: /// @brief Determines & sets effective config for data_mask /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note Datamask is unnused and not needed because no DBI. +/// @note Defaulted to 0 /// fapi2::ReturnCode eff_config::data_mask(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_data_mask(PORTS_PER_MCS, 0); // Targets @@ -2065,7 +2122,7 @@ fapi2::ReturnCode eff_config::data_mask(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( eff_data_mask(l_mcs, l_attrs_data_mask.data()) ); - l_attrs_data_mask[l_port_num] = 0x00; + l_attrs_data_mask[l_port_num] = fapi2::ENUM_ATTR_EFF_DATA_MASK_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DATA_MASK, l_mcs, @@ -2079,10 +2136,10 @@ fapi_try_exit: /// @brief Determines & sets effective config for write_dbi /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note DBI is not supported /// fapi2::ReturnCode eff_config::write_dbi(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_write_dbi(PORTS_PER_MCS, 0); // Targets @@ -2094,7 +2151,7 @@ fapi2::ReturnCode eff_config::write_dbi(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( eff_write_dbi(l_mcs, l_attrs_write_dbi.data()) ); - l_attrs_write_dbi[l_port_num] = 0x00; + l_attrs_write_dbi[l_port_num] = fapi2::ENUM_ATTR_EFF_WRITE_DBI_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_WRITE_DBI, l_mcs, @@ -2109,17 +2166,18 @@ fapi_try_exit: /// @brief Determines & sets effective config for read_dbi /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note read_dbi is not supported, so set to DISABLED (0) +/// @note No logic for DBI /// fapi2::ReturnCode eff_config::read_dbi(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); std::vector<uint8_t> l_attrs_read_dbi(PORTS_PER_MCS, 0); FAPI_TRY( eff_read_dbi(l_mcs, l_attrs_read_dbi.data()) ); - l_attrs_read_dbi[l_port_num] = 0x00; + l_attrs_read_dbi[l_port_num] = fapi2::ENUM_ATTR_EFF_READ_DBI_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_READ_DBI, l_mcs, @@ -2134,10 +2192,11 @@ fapi_try_exit: /// @brief Determines & sets effective config for Post Package Repair /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note write_dbi is not supported, so set to DISABLED (0) +/// @note no logic for DBI /// fapi2::ReturnCode eff_config::post_package_repair(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); const auto l_dimm_num = index(i_target); @@ -2187,8 +2246,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::read_preamble(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_rd_preamble(PORTS_PER_MCS, 0); + uint8_t l_preamble = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); @@ -2197,9 +2256,22 @@ fapi2::ReturnCode eff_config::read_preamble(const fapi2::Target<TARGET_TYPE_DIMM // Current index const auto l_port_num = index(l_mca); + FAPI_TRY (vpd_mt_preamble (l_mca, l_preamble) ) ; + l_preamble = l_preamble & 0xF0; + l_preamble = l_preamble >> 4; + + + FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), + fapi2::MSS_INVALID_VPD_MT_PREAMBLE() + .set_VALUE(l_preamble) + .set_DIMM_TARGET(i_target), + "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", + c_str(i_target), + l_preamble ); + FAPI_TRY( eff_rd_preamble(l_mcs, l_attrs_rd_preamble.data()) ); - l_attrs_rd_preamble[l_port_num] = 0x00; + l_attrs_rd_preamble[l_port_num] = l_preamble; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_RD_PREAMBLE, l_mcs, @@ -2217,9 +2289,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::write_preamble(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_wr_preamble(PORTS_PER_MCS, 0); - + uint8_t l_preamble = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); @@ -2227,14 +2298,26 @@ fapi2::ReturnCode eff_config::write_preamble(const fapi2::Target<TARGET_TYPE_DIM // Current index const auto l_port_num = index(l_mca); + FAPI_TRY (vpd_mt_preamble (l_mca, l_preamble) ) ; + l_preamble = l_preamble & 0x0F; + FAPI_INF("WR preamble is %d", l_preamble); + + FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), + fapi2::MSS_INVALID_VPD_MT_PREAMBLE() + .set_VALUE(l_preamble) + .set_DIMM_TARGET(i_target), + "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", + c_str(i_target), + l_preamble ); + FAPI_TRY( eff_wr_preamble(l_mcs, l_attrs_wr_preamble.data()) ); - l_attrs_wr_preamble[l_port_num] = 0x00; + l_attrs_wr_preamble[l_port_num] = l_preamble; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_WR_PREAMBLE, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_wr_preamble, PORTS_PER_MCS)), - "Failed setting attribute for WR_PREAMBLE"); + "Failed setting attribute for RD_PREAMBLE"); fapi_try_exit: return fapi2::current_err; @@ -2247,7 +2330,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::self_refresh_abort(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_self_ref_abort(PORTS_PER_MCS, 0); // Targets @@ -2259,7 +2341,7 @@ fapi2::ReturnCode eff_config::self_refresh_abort(const fapi2::Target<TARGET_TYPE FAPI_TRY( eff_self_ref_abort(l_mcs, l_attrs_self_ref_abort.data()) ); - l_attrs_self_ref_abort[l_port_num] = 0x00; + l_attrs_self_ref_abort[l_port_num] = fapi2::ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_SELF_REF_ABORT, l_mcs, @@ -2270,7 +2352,6 @@ fapi_try_exit: return fapi2::current_err; } - /// /// @brief Determines & sets effective config for cs_cmd_latency /// @param[in] i_target FAPI2 target @@ -2278,7 +2359,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::cs_to_cmd_addr_latency(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_cs_cmd_latency(PORTS_PER_MCS, 0); // Targets @@ -2290,7 +2370,7 @@ fapi2::ReturnCode eff_config::cs_to_cmd_addr_latency(const fapi2::Target<TARGET_ FAPI_TRY( eff_cs_cmd_latency(l_mcs, l_attrs_cs_cmd_latency.data()) ); - l_attrs_cs_cmd_latency[l_port_num] = 0x00; + l_attrs_cs_cmd_latency[l_port_num] = fapi2::ENUM_ATTR_EFF_CS_CMD_LATENCY_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_CS_CMD_LATENCY, l_mcs, @@ -2308,7 +2388,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::internal_vref_monitor(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_int_vref_mon(PORTS_PER_MCS, 0); // Targets @@ -2320,7 +2399,7 @@ fapi2::ReturnCode eff_config::internal_vref_monitor(const fapi2::Target<TARGET_T FAPI_TRY( eff_internal_vref_monitor(l_mcs, l_attrs_int_vref_mon.data()) ); - l_attrs_int_vref_mon[l_port_num] = 0x00; + l_attrs_int_vref_mon[l_port_num] = fapi2::ENUM_ATTR_EFF_INTERNAL_VREF_MONITOR_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_INTERNAL_VREF_MONITOR, l_mcs, @@ -2338,7 +2417,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::max_powerdown_mode(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint8_t> l_attrs_powerdown_mode(PORTS_PER_MCS, 0); // Targets @@ -2350,7 +2428,7 @@ fapi2::ReturnCode eff_config::max_powerdown_mode(const fapi2::Target<TARGET_TYPE FAPI_TRY( eff_max_powerdown_mode(l_mcs, l_attrs_powerdown_mode.data()) ); - l_attrs_powerdown_mode[l_port_num] = 0x00; + l_attrs_powerdown_mode[l_port_num] = fapi2::ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_MAX_POWERDOWN_MODE, l_mcs, @@ -2604,7 +2682,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::write_crc(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //TODO: RTC 159554 Update RAS related attributes std::vector<uint8_t> l_attrs_write_crc(PORTS_PER_MCS, 0); // Targets @@ -2616,7 +2694,7 @@ fapi2::ReturnCode eff_config::write_crc(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( eff_write_crc(l_mcs, l_attrs_write_crc.data()) ); - l_attrs_write_crc[l_port_num] = 0x00; + l_attrs_write_crc[l_port_num] = fapi2::ENUM_ATTR_EFF_WRITE_CRC_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_WRITE_CRC, l_mcs, @@ -2634,8 +2712,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint32_t> l_attrs_zqcal_interval(PORTS_PER_MCS, 0); + uint64_t l_freq = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); @@ -2644,15 +2722,17 @@ fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<TARGET_TYPE_DIM // Current index const auto l_port_num = index(l_mca); + FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(l_mcs), l_freq)); FAPI_TRY( eff_zqcal_interval(l_mcs, l_attrs_zqcal_interval.data()) ); - // Calculate ZQCAL Interval based on the following equation from Ken: // 0.5 // ------------------------------ = 13.333ms // (1.5 * 10) + (0.15 * 150) // (13333 * ATTR_MSS_FREQ) / 2 - l_attrs_zqcal_interval[l_port_num] = 0xF42270; + + l_attrs_zqcal_interval[l_port_num] = 13333 * l_freq / 2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_ZQCAL_INTERVAL, l_mcs, @@ -2670,8 +2750,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::memcal_interval(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM std::vector<uint32_t> l_attrs_memcal_interval(PORTS_PER_MCS, 0); + uint64_t l_freq = 0; // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); @@ -2680,11 +2760,13 @@ fapi2::ReturnCode eff_config::memcal_interval(const fapi2::Target<TARGET_TYPE_DI // Current index const auto l_port_num = index(l_mca); + FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq)); + FAPI_TRY( eff_memcal_interval(l_mcs, l_attrs_memcal_interval.data()) ); // Calculate MEMCAL Interval based on 1sec interval across all bits per DP16 // (62500 * ATTR_MSS_FREQ) / 2 - l_attrs_memcal_interval[l_port_num] = 0x47868C0; + l_attrs_memcal_interval[l_port_num] = 62500 * l_freq / 2; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_MEMCAL_INTERVAL, l_mcs, @@ -2724,24 +2806,18 @@ fapi2::ReturnCode eff_config::dram_trp(const fapi2::Target<TARGET_TYPE_DIMM>& i_ { std::vector<uint8_t> l_attrs_dram_trp(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_trp_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_trp_in_nck = 0; // Calculate nck - l_trp_in_nck = calc_nck(l_trp_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_trp_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trp_in_nck), + "Error in calculating dram_tRP nck for target %s, with value of l_trp_in_ps: %d", mss::c_str(i_target), l_trp_in_ps); - FAPI_INF("Calculated tRP (nck): %d", l_trp_in_nck); + FAPI_INF("Calculated trp (ps): %d, trp (nck): %d for target: %s", l_trp_in_ps, l_trp_in_nck, mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_trp(l_mcs, l_attrs_dram_trp.data()) ); - l_attrs_dram_trp[l_port_num] = uint8_t( l_trp_in_nck ); + l_attrs_dram_trp[l_port_num] = l_trp_in_nck ; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRP, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_trp, PORTS_PER_MCS)), @@ -2774,26 +2850,20 @@ fapi2::ReturnCode eff_config::dram_trcd(const fapi2::Target<TARGET_TYPE_DIMM>& i FAPI_TRY( iv_pDecoder->fine_timebase(i_target, l_ftb) ); FAPI_TRY( iv_pDecoder->min_ras_to_cas_delay_time(i_target, l_trcd_mtb) ); FAPI_TRY( iv_pDecoder->fine_offset_min_trcd(i_target, l_trcd_ftb) ); - + FAPI_INF( "trcd values are: min_trcd %d, fine offset is %d", l_trcd_mtb, l_trcd_ftb); l_trcd_in_ps = calc_timing_from_timebase(l_trcd_mtb, l_mtb, l_trcd_ftb, l_ftb); } { std::vector<uint8_t> l_attrs_dram_trcd(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_trcd_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_trcd_in_nck = 0; // Calculate nck - l_trcd_in_nck = calc_nck(l_trcd_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_trcd_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trcd_in_nck), + "Error in calculating trcd for target %s, with value of l_trcd_in_ps: %d", mss::c_str(i_target), l_trcd_in_ps); - FAPI_INF("Calculated trcd (nck): %d", l_trcd_in_nck); + FAPI_INF("Calculated trcd (ps): %d, trcd (nck): %d for target: %s", l_trcd_in_ps, l_trcd_in_nck, mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_trcd(l_mcs, l_attrs_dram_trcd.data()) ); @@ -2837,24 +2907,19 @@ fapi2::ReturnCode eff_config::dram_twtr_l(const fapi2::Target<TARGET_TYPE_DIMM>& { std::vector<uint8_t> l_attrs_dram_twtr_l(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_twtr_l_in_nck = 0; + int8_t l_twtr_l_in_nck = 0; - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); - - // Calculate nck - l_twtr_l_in_nck = calc_nck(l_twtr_l_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + // Calculate tNCK + FAPI_TRY( calc_nck(l_twtr_l_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_twtr_l_in_nck), + "Error in calculating twtr_l for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_twtr_l_in_ps ); - FAPI_INF("Calculated twtr_l (nck): %d", l_twtr_l_in_nck); + FAPI_INF("Calculated twtr_l (ps): %d, twtr_l (nck): %d for target: %s", l_twtr_l_in_ps, l_twtr_l_in_nck, + mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_twtr_l(l_mcs, l_attrs_dram_twtr_l.data()) ); - l_attrs_dram_twtr_l[l_port_num] = uint8_t( l_twtr_l_in_nck ); + l_attrs_dram_twtr_l[l_port_num] = l_twtr_l_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TWTR_L, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_twtr_l, PORTS_PER_MCS)), @@ -2892,24 +2957,19 @@ fapi2::ReturnCode eff_config::dram_twtr_s(const fapi2::Target<TARGET_TYPE_DIMM>& { std::vector<uint8_t> l_attrs_dram_twtr_s(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_twtr_s_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_twtr_s_in_nck = 0; // Calculate nck - l_twtr_s_in_nck = calc_nck(l_twtr_s_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_twtr_s_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_twtr_s_in_nck), + "Error in calculating l_twtr_s for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_twtr_s_in_ps); - FAPI_INF("Calculated twtr_s (nck): %d", l_twtr_s_in_nck); + FAPI_INF("Calculated twtr_s (ps): %d, twtr_s (nck): %d for target: %s", l_twtr_s_in_ps, l_twtr_s_in_nck, + mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_twtr_s(l_mcs, l_attrs_dram_twtr_s.data()) ); - l_attrs_dram_twtr_s[l_port_num] = uint8_t( l_twtr_s_in_nck ); + l_attrs_dram_twtr_s[l_port_num] = l_twtr_s_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TWTR_S, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_twtr_s, PORTS_PER_MCS)), @@ -2948,24 +3008,18 @@ fapi2::ReturnCode eff_config::dram_trrd_s(const fapi2::Target<TARGET_TYPE_DIMM>& { std::vector<uint8_t> l_attrs_dram_trrd_s(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_trrd_s_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_trrd_s_in_nck = 0; // Calculate nck - l_trrd_s_in_nck = calc_nck(l_trrd_s_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); - - FAPI_INF("Calculated trrd_s (nck): %d", l_trrd_s_in_nck); + FAPI_TRY( calc_nck(l_trrd_s_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trrd_s_in_nck), + "Error in calculating trrd_s for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_trrd_s_in_ps); + FAPI_INF("Calculated trrd_s (ps): %d, trrd_s (nck): %d for target: %s", l_trrd_s_in_ps, l_trrd_s_in_nck, + mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_trrd_s(l_mcs, l_attrs_dram_trrd_s.data()) ); - l_attrs_dram_trrd_s[l_port_num] = uint8_t( l_trrd_s_in_nck ); + l_attrs_dram_trrd_s[l_port_num] = l_trrd_s_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRRD_S, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_trrd_s, PORTS_PER_MCS)), @@ -3004,24 +3058,19 @@ fapi2::ReturnCode eff_config::dram_trrd_l(const fapi2::Target<TARGET_TYPE_DIMM>& { std::vector<uint8_t> l_attrs_dram_trrd_l(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_trrd_l_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_trrd_l_in_nck = 0; // Calculate nck - l_trrd_l_in_nck = calc_nck(l_trrd_l_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_trrd_l_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trrd_l_in_nck), + "Error in calculating trrd_l for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_trrd_l_in_ps); - FAPI_INF("Calculated trrd_l (nck): %d", l_trrd_l_in_nck); + FAPI_INF("Calculated trrd_l (ps): %d, trrd_l (nck): %d for target: %s", l_trrd_l_in_ps, l_trrd_l_in_nck, + mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_trrd_l(l_mcs, l_attrs_dram_trrd_l.data()) ); - l_attrs_dram_trrd_l[l_port_num] = uint8_t( l_trrd_l_in_nck ); + l_attrs_dram_trrd_l[l_port_num] = l_trrd_l_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRRD_L, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_trrd_l, PORTS_PER_MCS)), @@ -3059,24 +3108,18 @@ fapi2::ReturnCode eff_config::dram_tfaw(const fapi2::Target<TARGET_TYPE_DIMM>& i { std::vector<uint8_t> l_attrs_dram_tfaw(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_tfaw_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + uint8_t l_tfaw_in_nck = 0; // Calculate nck - l_tfaw_in_nck = calc_nck(l_tfaw_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY ( calc_nck(l_tfaw_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_tfaw_in_nck), + "Error in calculating tfaw_l for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_tfaw_in_ps ); - FAPI_INF("Calculated tfaw (nck): %d", l_tfaw_in_nck); + FAPI_INF("Calculated tFAW (ps): %d, tFAW (nck): %d for target: %s", l_tfaw_in_ps, l_tfaw_in_nck, mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_tfaw(l_mcs, l_attrs_dram_tfaw.data()) ); - l_attrs_dram_tfaw[l_port_num] = uint8_t( l_tfaw_in_nck ); + l_attrs_dram_tfaw[l_port_num] = l_tfaw_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TFAW, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_tfaw, PORTS_PER_MCS)), @@ -3094,7 +3137,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::dram_tras(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index(find_target<TARGET_TYPE_MCA>(i_target)); int64_t l_tras_in_ps = 0; @@ -3115,24 +3157,18 @@ fapi2::ReturnCode eff_config::dram_tras(const fapi2::Target<TARGET_TYPE_DIMM>& i { std::vector<uint8_t> l_attrs_dram_tras(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; - int64_t l_tras_in_nck = 0; - - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); + int8_t l_tras_in_nck = 0; // Calculate nck - l_tras_in_nck = calc_nck(l_tras_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_tras_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_tras_in_nck), + "Error in calculating tras_l for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_tras_in_ps); - FAPI_INF("Calculated tras (nck): %d", l_tras_in_nck); + FAPI_INF("Calculated tRAS (ps): %d, tRAS (nck): %d for target: %s", l_tras_in_ps, l_tras_in_nck, mss::c_str(i_target)); // Get & update MCS attribute FAPI_TRY( eff_dram_tras(l_mcs, l_attrs_dram_tras.data()) ); - l_attrs_dram_tras[l_port_num] = uint8_t( l_tras_in_nck ); + l_attrs_dram_tras[l_port_num] = l_tras_in_nck; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRAS, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_attrs_dram_tras, PORTS_PER_MCS)), @@ -3160,17 +3196,11 @@ fapi2::ReturnCode eff_config::dram_trtp(const fapi2::Target<TARGET_TYPE_DIMM>& i constexpr int64_t l_min_trtp_in_nck = 4; std::vector<uint8_t> l_attrs_dram_trtp(PORTS_PER_MCS, 0); - int64_t l_tCK_in_ps = 0; int64_t l_calc_trtp_in_nck = 0; - // Calculate clock period (tCK) from selected freq from mss_freq - FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); - FAPI_INF("Calculated clock period (tCK): %d", l_tCK_in_ps); - // Calculate nck - l_calc_trtp_in_nck = calc_nck(l_max_trtp_in_ps, - l_tCK_in_ps, - int64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + FAPI_TRY( calc_nck(l_max_trtp_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_calc_trtp_in_nck), + "Error in calculating trtp for target %s, with value of l_twtr_in_ps: %d", mss::c_str(i_target), l_max_trtp_in_ps); FAPI_INF("Calculated trtp (nck): %d", l_calc_trtp_in_nck); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H index cf1bf2694..f1531e279 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H @@ -44,6 +44,9 @@ // mss lib #include <lib/spd/common/spd_decoder.H> +#include <lib/eff_config/timing.H> +#include <lib/utils/conversions.H> +#include <lib/utils/find.H> namespace mss { @@ -53,26 +56,44 @@ namespace mss /// class eff_config { + private: + + int64_t iv_tCK_in_ps; + public: //TK - Make this constructor take this as param - AAM std::shared_ptr<spd::decoder> iv_pDecoder; - // TK - Adding decoder in ctor can allow me to save off the - // state of decoder timebases, target, fapi2 positions, - // and clock period eliminate code duplication. + //TODO: RTC 159777: Change eff_config class to use iv's for mcs, port and dimm position + + /// + /// @brief Constructor + /// @param[in] i_target, the fapi2::Target which we're configuring (DIMM) + /// @param[out] o_rc, a return code which determines the success of the constructor + /// + eff_config( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ) + { + FAPI_TRY( clock_period(i_target, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" ); + FAPI_INF("Calculated clock period (tCK): %d on DIMM %s", iv_tCK_in_ps, mss::c_str(i_target)); + + fapi_try_exit: + o_rc = fapi2::current_err; + return; + } /// /// @brief Constructor - /// @tparam T, the fapi2::TargetType of the target - /// @param[in] i_target, the fapi2::Target which we're configuring + /// @param[in] i_target the fapi2::Target which we're configuring (MCS) /// @param[out] o_rc, a return code which determines the success of the constructor /// - template< fapi2::TargetType T > - eff_config( const fapi2::Target<T>& i_target, fapi2::ReturnCode& o_rc ) + eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, fapi2::ReturnCode& o_rc ) { - // Leaving the fapi2::RaturnCode scaffolding in place as we'll likely need it - // in the future and this way it will be here. BRS - o_rc = fapi2::FAPI2_RC_SUCCESS; + FAPI_TRY( clock_period(i_target, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" ); + FAPI_INF("Calculated clock period (tCK): %d on DIMM %s", iv_tCK_in_ps, mss::c_str(i_target)); + + fapi_try_exit: + o_rc = fapi2::current_err; + return; } // @@ -192,13 +213,6 @@ class eff_config fapi2::ReturnCode master_ranks_per_dimm(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); /// - /// @brief Determines & sets effective config for custom dimm - /// @param[in] i_target FAPI2 target - /// @return fapi2::FAPI2_RC_SUCCESS if okay - /// - fapi2::ReturnCode custom_dimm(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); - - /// /// @brief Determines & sets effective config for tDQS /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay @@ -404,13 +418,6 @@ class eff_config fapi2::ReturnCode dram_twr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); /// - /// @brief Determines & sets effective config for burst length (BL) - /// @param[in] i_target FAPI2 target - /// @return fapi2::FAPI2_RC_SUCCESS if okay - /// - fapi2::ReturnCode burst_length(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); - - /// /// @brief Determines & sets effective config for RBT /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay @@ -438,7 +445,6 @@ class eff_config /// fapi2::ReturnCode dram_lpasr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); - /// /// @brief Determines & sets effective config for additive latency /// @param[in] i_target FAPI2 target @@ -530,7 +536,6 @@ class eff_config /// @return fapi2::FAPI2_RC_SUCCESS if okay /// fapi2::ReturnCode odt_input_buffer(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); - /// /// @brief Determines & sets effective config for data_mask /// @param[in] i_target FAPI2 target @@ -765,5 +770,4 @@ class eff_config }; // eff_config } // mss - #endif // _MSS_EFF_CONFIG_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C index b755dfbd8..e87a0457e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C @@ -72,6 +72,7 @@ static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR4 = // 16Gb - TBD }; +/// /// @brief Calculates refresh interval time /// @param[in] i_mode fine refresh rate mode /// @param[in] i_temp_refresh_range temperature refresh range @@ -80,9 +81,9 @@ static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR4 = /// fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, const uint8_t i_temp_refresh_range, - uint64_t& o_timing ) + int64_t& o_timing ) { - uint64_t l_multiplier = 0; + int64_t l_multiplier = 0; switch(i_temp_refresh_range) { @@ -103,8 +104,8 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, break; } - const uint64_t l_quotient = TREFI_BASE / ( uint64_t(i_mode) * l_multiplier ); - const uint64_t l_remainder = TREFI_BASE % ( uint64_t(i_mode) * l_multiplier ); + const int64_t l_quotient = TREFI_BASE / ( int64_t(i_mode) * l_multiplier ); + const int64_t l_remainder = TREFI_BASE % ( int64_t(i_mode) * l_multiplier ); o_timing = l_quotient + (l_remainder == 0 ? 0 : 1); FAPI_INF( "tREFI: %d, quotient: %d, remainder: %d, tREFI_base: %d", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H index 9a207865b..894205480 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H @@ -37,11 +37,12 @@ #include <cstdint> #include <fapi2.H> - +#include <lib/utils/find.H> +#include <lib/utils/conversions.H> namespace mss { -enum GUARD_BAND : size_t +enum GUARD_BAND : uint16_t { // Used for caclulating spd timing values - from JEDEC rounding algorithm // Correction factor is 1% (for DDR3) or 2.5% (for DDR4) @@ -87,26 +88,40 @@ inline int64_t calc_timing_from_timebase(const int64_t i_timing_mtb, /// /// @brief Returns clock cycles -/// @tparam T input and output type +/// @tparam T input +/// @tparam OT output /// @param[in] timing_in_ps timing parameter in ps /// @param[in] tck_in_ps clock period in ps /// @param[in] inverse_corr_factor inverse correction factor (defined by JEDEC) +/// @param[out] o_value_nck the end calculation in nck /// @return the clock cycles of timing parameter (provided in ps) /// @note DDR4 SPD Contents Rounding Algorithm /// @note Item 2220.46 /// -template<typename T> -inline T calc_nck(const T i_timing_in_ps, - const T i_tck_in_ps, - const T i_inverse_corr_factor) +template<typename T, typename OT> +inline fapi2::ReturnCode calc_nck(const T& i_timing_in_ps, + const T& i_tck_in_ps, + GUARD_BAND i_inverse_corr_factor, + OT& o_val_nck) { // Preliminary nCK calculation, scaled by 1000 per JDEC algorithm T l_temp_nck = (i_timing_in_ps * 1000) / (i_tck_in_ps == 0 ? 1 : i_tck_in_ps); - - // Apply inverse of correction factor percentage l_temp_nck += i_inverse_corr_factor; + l_temp_nck = l_temp_nck / 1000; + + //Check for overflow. + o_val_nck = l_temp_nck; + + FAPI_ASSERT(o_val_nck == l_temp_nck, + fapi2::MSS_INVALID_CAST_CALC_NCK(). + set_TIMING_PS(i_timing_in_ps). + set_NCK_NS(i_tck_in_ps). + set_CORRECTION_FACTOR(i_inverse_corr_factor), + "Bad cast for calc_nck. Output is: %d, after cast is %d", l_temp_nck, l_temp_nck); + return fapi2::FAPI2_RC_SUCCESS; - return l_temp_nck / 1000; +fapi_try_exit: + return fapi2::current_err; } /// @@ -138,7 +153,7 @@ fapi_try_exit: /// fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, const uint8_t i_temp_refresh_range, - uint64_t& o_timing ); + int64_t& o_timing ); /// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) /// @param[in] i_mode fine refresh rate mode @@ -151,5 +166,4 @@ fapi2::ReturnCode calc_trfc_dlr( const uint8_t i_refresh_mode, uint64_t& o_trfc_in_ps ); } // mss - #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index a03734867..432df773c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -239,99 +239,6 @@ fapi_try_exit: } /// -/// @brief ATTR_EFF_CUSTOM_DIMM getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we -/// could support Custom DIMMs of different types than an UDIMM, such as RDIMM and -/// LRDIMM. Created in mss_eff_cnfg Use this attribute if you need to know if the -/// Centaur is on the DIMM instead of on a -/// planar. -/// -inline fapi2::ReturnCode eff_custom_dimm(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) -{ - uint8_t l_value[2][2]; - auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_CUSTOM_DIMM, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_CUSTOM_DIMM: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_EFF_CUSTOM_DIMM getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we -/// could support Custom DIMMs of different types than an UDIMM, such as RDIMM and -/// LRDIMM. Created in mss_eff_cnfg Use this attribute if you need to know if the -/// Centaur is on the DIMM instead of on a -/// planar. -/// -inline fapi2::ReturnCode eff_custom_dimm(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; - auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_CUSTOM_DIMM, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_CUSTOM_DIMM: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_EFF_CUSTOM_DIMM getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we -/// could support Custom DIMMs of different types than an UDIMM, such as RDIMM and -/// LRDIMM. Created in mss_eff_cnfg Use this attribute if you need to know if the -/// Centaur is on the DIMM instead of on a -/// planar. -/// -inline fapi2::ReturnCode eff_custom_dimm(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_CUSTOM_DIMM, i_target, l_value) ); - memcpy(o_array, &l_value, 4); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_CUSTOM_DIMM: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// /// @brief ATTR_EFF_DIMM_SPARE getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] uint8_t* memory to store the value @@ -762,88 +669,6 @@ fapi_try_exit: } /// -/// @brief ATTR_EFF_DRAM_BL getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Burst Length. Used in various locations and is computed in mss_eff_cnfg. Each -/// memory channel will have a value. creator: mss_eff_cnfg consumer: various -/// firmware notes: -/// none -/// -inline fapi2::ReturnCode eff_dram_bl(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) -{ - uint8_t l_value[2]; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_BL, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); - o_value = l_value[mss::index(i_target)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_DRAM_BL: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_EFF_DRAM_BL getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Burst Length. Used in various locations and is computed in mss_eff_cnfg. Each -/// memory channel will have a value. creator: mss_eff_cnfg consumer: various -/// firmware notes: -/// none -/// -inline fapi2::ReturnCode eff_dram_bl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) -{ - uint8_t l_value[2]; - auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_BL, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); - o_value = l_value[mss::index(l_mca)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_DRAM_BL: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_EFF_DRAM_BL getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Burst Length. Used in various locations and is computed in mss_eff_cnfg. Each -/// memory channel will have a value. creator: mss_eff_cnfg consumer: various -/// firmware notes: -/// none -/// -inline fapi2::ReturnCode eff_dram_bl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2]; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_BL, i_target, l_value) ); - memcpy(o_array, &l_value, 2); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_EFF_DRAM_BL: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// /// @brief ATTR_EFF_DRAM_CL getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 16ae28482..0333ed464 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -600,7 +600,6 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) uint8_t l_wlo = 0; uint8_t l_dram_gen[MAX_DIMM_PER_PORT] = {0}; uint8_t l_dimm_type[MAX_DIMM_PER_PORT] = {0}; - uint8_t l_custom_dimm[MAX_DIMM_PER_PORT] = {0}; uint8_t l_type_index = 0; uint8_t l_gen_index = 0; @@ -608,13 +607,11 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) FAPI_TRY( mss::vpd_wlo(i_target, l_wlo) ); FAPI_TRY( mss::eff_dram_gen(i_target, &(l_dram_gen[0])) ); FAPI_TRY( mss::eff_dimm_type(i_target, &(l_dimm_type[0])) ); - FAPI_TRY( mss::eff_custom_dimm(i_target, &(l_custom_dimm[0])) ); // There's no way to configure the PHY for more than one value. However, we don't know if there's // a DIMM in one slot, the other or double drop. So we do a little gyration here to make sure - // we have one of the two values (and assume effective config caught a bad config.) - l_type_index = (l_custom_dimm[0] | l_custom_dimm[1]) == fapi2::ENUM_ATTR_EFF_CUSTOM_DIMM_YES ? - 2 : l_dimm_type[0] | l_dimm_type[1]; + // we have one of the two values (and assume effective config caught a bad config + l_type_index = l_dimm_type[0] | l_dimm_type[1]; l_gen_index = l_dram_gen[0] | l_dram_gen[1]; // FOR NIMBUS PHY (as the protocol choice above is) BRS diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 273b46956..bd607b2f0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -310,7 +310,7 @@ typedef std::vector< register_data_pair > register_data_vector; // to see the bits like this than in a more compact algorithmic arrangement. // Systems without Spare Bytes (or with deconfigured spares) -static std::vector< register_data_vector > data_bit_enable_no_spare = +static const register_data_vector data_bit_enable_no_spare[] = { // DHPY01 { @@ -329,7 +329,7 @@ static std::vector< register_data_vector > data_bit_enable_no_spare = }; // Rank Pair will be added to the register address before writing -static std::vector< register_data_vector > wrclk_enable_no_spare_x4 = +static const register_data_vector wrclk_enable_no_spare_x4[] = { { {MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x8640}, @@ -341,7 +341,7 @@ static std::vector< register_data_vector > wrclk_enable_no_spare_x4 = }; // Rank Pair will be added to the register address before writing -static std::vector< register_data_vector > rdclk_enable_no_spare_x4 = +static const register_data_vector rdclk_enable_no_spare_x4[] = { { {MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x8640}, @@ -353,7 +353,7 @@ static std::vector< register_data_vector > rdclk_enable_no_spare_x4 = }; // Systems With Spare Bytes Enabled -static std::vector< register_data_vector > data_bit_enable_spare = +static const register_data_vector data_bit_enable_spare[] = { // DHPY01 { @@ -371,7 +371,7 @@ static std::vector< register_data_vector > data_bit_enable_spare = }, }; -static std::vector< register_data_vector > wrclk_enable_spare_x4 = +static const register_data_vector wrclk_enable_spare_x4[] = { { {MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x8640}, @@ -382,7 +382,7 @@ static std::vector< register_data_vector > wrclk_enable_spare_x4 = }, }; -static std::vector< register_data_vector > rdclk_enable_spare_x4 = +static const register_data_vector rdclk_enable_spare_x4[] = { { {MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x8640}, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H index 30aa7f6bb..cadca6a20 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H @@ -358,30 +358,19 @@ fapi_try_exit: /// @brief reset rc_config2 /// @param[in] i_target fapi2 target of the port /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// @note Burst length is always BL8 /// template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_data; - uint8_t is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) ); // Bogus Centaur SIM number from init file - use 8 per Bialas 2/16 // ---48:52, 0b00000, (def_is_sim); # CONSEQ_PASS sim value--- // 48:52, 0b01000, (def_is_bl8); # CONSEQ_PASS 8 from SWyatt // 48:52, 0b01111, any; # CONSEQ_PASS 16 min for BL4, or OTF - if (is_sim) - { - l_data.insertFromRight<TT::CONSEQ_PASS, TT::CONSEQ_PASS_LEN>(0b01000); - } - else - { - uint8_t l_bl = 0; - - FAPI_TRY( mss::eff_dram_bl(i_target, l_bl) ); - l_data.insertFromRight<TT::CONSEQ_PASS, TT::CONSEQ_PASS_LEN>( - l_bl == fapi2::ENUM_ATTR_EFF_DRAM_BL_BL8 ? 0b01000 : 0b01111); - } + + l_data.insertFromRight<TT::CONSEQ_PASS, TT::CONSEQ_PASS_LEN>( 0b01000 ); // 57:58, 0b11, any; # BURST_WINDOW, compare all 8 beats (AS recommended) l_data.insertFromRight<TT::BURST_WINDOW, TT::BURST_WINDOW_LEN>(0b11); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C index 0af1e912c..9ce5f2e63 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C @@ -2279,10 +2279,11 @@ fapi2::ReturnCode decoder::min_write_recovery_time(const fapi2::Target<TARGET_TY { // For General Section rev 1.0 of the SPD, // SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) were reserved - // and coded as zeros. There was no concept of - // min write recovery time so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x78 for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x78; return fapi2::FAPI2_RC_SUCCESS; } @@ -2302,9 +2303,11 @@ fapi2::ReturnCode decoder::min_twtr_s(const fapi2::Target<TARGET_TYPE_DIMM>& i_t { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 3~0) & Byte 44 (bits 7~0) were reserved - // and coded as zeros. There was no concept of twtr_s so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x14 for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x14; return fapi2::FAPI2_RC_SUCCESS; } @@ -2323,9 +2326,11 @@ fapi2::ReturnCode decoder::min_twtr_l(const fapi2::Target<TARGET_TYPE_DIMM>& i_t { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 7~4) & Byte 45 (bits 7~0) were reserved - // and coded as zeros. There was no concept of twtr_l so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x3C for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x3C; return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C index 97159c5cd..49e8c28a7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C @@ -83,7 +83,7 @@ static constexpr uint8_t vbu_spd[] = //16 0x00, 0x00, 0x07, 0x0D, 0xF8, 0x7F, 0x00, 0x00, 0x6B, 0x6B, 0x6B, 0x11, 0x00, 0x6E, 0xF0, 0x0A, //32 - 0x20, 0x08, 0x00, 0x05, 0x00, 0x68, 0x1B, 0x28, 0x28, 0x00, 0x00, 0x00, 0x14, 0x3C, 0x00, 0x00, + 0x20, 0x08, 0x00, 0x05, 0x00, 0x68, 0x1B, 0x28, 0x28, 0x00, 0x78, 0x00, 0x14, 0x3C, 0x00, 0x00, //48 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x03, 0x15, 0x2C, //64 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C index 5c9982d38..d340b760a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C @@ -56,7 +56,7 @@ static constexpr uint8_t raw_mt[raw_mt_size] = 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x16, 0x16, 0x00, 0x01, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x16, 0x00, 0x01, 0x31, 0xfd, 0x00, 0x01, 0x31, 0xfd, 0x80, 0x23, 0x80, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H index b8a6563ac..4b113a5ab 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H @@ -313,6 +313,41 @@ bool find_value_from_key(const std::vector<std::pair<T, OT> >& i_vector_of_pairs }// find_value_from_key /// +/// @brief find a key value from a C-style array of STL pairs +/// @tparam T input type +/// @tparam OT the output type to be returned +/// @tparam N size of the array being passed in +/// @param[in] i_array the input array of pairs +/// @param[in] i_key the "map" key +/// @param[in] o_value the value found from given key +/// @return the value corresponding to the key +/// @note To use on short arrays. O(N), simple search +/// + +template<typename T, typename OT, size_t N> +fapi2::ReturnCode find_value_from_key( const std::pair<T, OT> (&i_array)[N], const T& i_key, OT& o_value) +{ + // TK Use sort and binary search for larger arrays + if (i_array == nullptr) + { + FAPI_ERR("nullptr passed to the find_value_from_key function"); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + for (size_t i = 0; i < N; i++) + { + if (i_array[i].first == i_key) + { + o_value = i_array[i].second; + return fapi2::FAPI2_RC_SUCCESS; + } + } + + FAPI_ERR ("No match found for find_value_from_key"); + return fapi2::FAPI2_RC_INVALID_PARAMETER; +} + +/// /// @brief Determine if a thing is functional /// @tparam P, the type of the parent which holds the things of interest /// @tparam I, the type of the item we want to check for diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index fd1867bbe..4589c5fa4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -122,10 +122,8 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY( l_eff_config.rcd_mirror_mode(l_dimm) ); FAPI_TRY( l_eff_config.dram_bank_bits(l_dimm) ); FAPI_TRY( l_eff_config.dram_row_bits(l_dimm) ); - FAPI_TRY( l_eff_config.custom_dimm(l_dimm) ); FAPI_TRY( l_eff_config.dram_dqs_time(l_dimm) ); FAPI_TRY( l_eff_config.dram_tccd_l(l_dimm) ); - FAPI_TRY( l_eff_config.data_mask(l_dimm) ); FAPI_TRY( l_eff_config.dimm_rc00(l_dimm) ); FAPI_TRY( l_eff_config.dimm_rc01(l_dimm) ); FAPI_TRY( l_eff_config.dimm_rc02(l_dimm) ); @@ -153,12 +151,10 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY( l_eff_config.dimm_rcax(l_dimm) ); FAPI_TRY( l_eff_config.dimm_rcbx(l_dimm) ); FAPI_TRY( l_eff_config.dram_twr(l_dimm) ); - FAPI_TRY( l_eff_config.burst_length(l_dimm) ); FAPI_TRY( l_eff_config.read_burst_type(l_dimm) ); FAPI_TRY( l_eff_config.dram_tm(l_dimm) ); FAPI_TRY( l_eff_config.dram_cwl(l_dimm) ); FAPI_TRY( l_eff_config.dram_lpasr(l_dimm) ); - FAPI_TRY( l_eff_config.additive_latency(l_dimm) ); FAPI_TRY( l_eff_config.dll_enable(l_dimm) ); FAPI_TRY( l_eff_config.dll_reset(l_dimm) ); FAPI_TRY( l_eff_config.write_level_enable(l_dimm) ); @@ -171,8 +167,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY( l_eff_config.ca_parity(l_dimm) ); FAPI_TRY( l_eff_config.crc_error_clear(l_dimm) ); FAPI_TRY( l_eff_config.odt_input_buffer(l_dimm) ); - FAPI_TRY( l_eff_config.write_dbi(l_dimm) ); - FAPI_TRY( l_eff_config.read_dbi(l_dimm) ); FAPI_TRY( l_eff_config.post_package_repair(l_dimm) ); FAPI_TRY( l_eff_config.read_preamble_train(l_dimm) ); FAPI_TRY( l_eff_config.read_preamble(l_dimm) ); @@ -200,7 +194,10 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY( l_eff_config.dram_tfaw(l_dimm) ); FAPI_TRY( l_eff_config.dram_tras(l_dimm) ); FAPI_TRY( l_eff_config.dram_trtp(l_dimm) ); - + FAPI_TRY( l_eff_config.read_dbi(l_dimm) ); + FAPI_TRY( l_eff_config.write_dbi(l_dimm) ); + FAPI_TRY( l_eff_config.additive_latency(l_dimm) ); + FAPI_TRY( l_eff_config.data_mask(l_dimm) ); // Hard-coded RIT protect attribute set (currently not taken account in eff_config) { uint16_t l_mss_vpd_mt_windage_rd_ctr[mss::PORTS_PER_MCS] = {0xDEAD, 0xBEEF}; |
