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path: root/llvm/utils/TableGen/CodeGenInstruction.cpp
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* [TableGen] Add EncoderMethod to RegisterOperandSam Kolton2017-05-151-0/+1
| | | | | | | | Reviewers: stoklund, grosbach, vpykhtin Differential Revision: https://reviews.llvm.org/D32493 llvm-svn: 303044
* TableGen: Use StringInit instead of std::string for DagInit arg namesMatthias Braun2016-12-051-16/+16
| | | | llvm-svn: 288644
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-2/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Apply clang-tidy's 'performance-faster-string-find' check to LLVM.Benjamin Kramer2016-11-301-1/+1
| | | | | | No functionality change intended. llvm-svn: 288235
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-0/+1
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* TableGen: Add hasNoSchedulingInfo to instructionsMatthias Braun2016-03-011-0/+1
| | | | | | | | | | | | | This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information. This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs. Differential Revision: http://reviews.llvm.org/D17728 llvm-svn: 262383
* Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)Reid Kleckner2016-02-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a reserve call to an expensive function (`llvm::LoadIntrinsics`), and may fix a few other low hanging performance fruit (I've put them in comments for now, so we can discuss). **Motivation:** As I'm sure other developers do, when I build LLVM, I build the entire project with the same config (`Debug`, `MinSizeRel`, `Release`, or `RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen in `Debug` mode. Later build steps that run llvm-tblgen then can actually be the slowest steps in the entire build. Nobody likes slow builds. Reviewers: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D16832 Patch by Alexander G. Riccio llvm-svn: 259683
* Add an OperandNamespace field to Target.td's Operand.Dan Gohman2015-12-221-0/+1
| | | | | | | | For targets to add their own operand types as needed, as advertised in Operand's comment, they need to be able to specify an alternate namespace for OperandType names too. This matches the RegisterOperand class. llvm-svn: 256299
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-291-6/+6
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* Add support for the convergent flag at the MC and MachineInstr levels.Owen Anderson2015-05-281-0/+1
| | | | llvm-svn: 238450
* Reverted 230471 - gather scatter handling in table gen.Elena Demikhovsky2015-03-011-1/+0
| | | | llvm-svn: 230892
* AVX-512: Gather and Scatter patternsElena Demikhovsky2015-02-251-0/+1
| | | | | | | | | | | | | | | Gather and scatter instructions additionally write to one of the source operands - mask register. In this case Gather has 2 destination values - the loaded value and the mask. Till now we did not support code gen pattern for gather - the instruction was generated from intrinsic only and machine node was hardcoded. When we introduce the masked_gather node, we need to select instruction automatically, in the standard way. I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands. (Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big patch in many small patches) llvm-svn: 230471
* Target: Allow target specific operand typesTom Stellard2015-01-121-2/+5
| | | | | | | | | | | | | | | | | | | This adds two new fields to the RegisterOperand TableGen class: string OperandNamespace = "MCOI"; string OperandType = "OPERAND_REGISTER"; These fields can be used to specify a target specific operand type, which will be stored in the OperandType member of the MCOperandInfo object. This can be useful for targets that need to store some extra information about operands that cannot be expressed using the target independent types. For example, in the R600 backend, there are operands which can take either registers or immediates and it is convenient to be able to specify this in the TableGen definitions. llvm-svn: 225661
* Clean up static analyzer warnings.Michael Ilseman2014-12-121-1/+1
| | | | | | | | | Clang's static analyzer found several potential cases of undefined behavior, use of un-initialized values, and potentially null pointer dereferences in tablegen, Support, MC, and ADT. This cleans them up with specific assertions on the assumptions of the code. llvm-svn: 224154
* Remove neverHasSideEffects support from TableGen CodeGenInstruction. ↵Craig Topper2014-11-261-4/+0
| | | | | | Everyone should use hasSideEffects now. llvm-svn: 222809
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+1
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* Change BitsInit to inherit from TypedInit.Pete Cooper2014-08-071-0/+15
| | | | | | This is useful in a later patch where binary literals such as 0b000 will become BitsInit values instead of IntInit values. llvm-svn: 215085
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-0/+17
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-2/+6
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-291-11/+11
| | | | | | No functionality change. llvm-svn: 205110
* TableGen: avoid dereferencing nullptr variableTim Northover2014-03-291-6/+10
| | | | | | | ARM64 ended up reaching odder parts of TableGen alias generation than current backends and caused a segfault. llvm-svn: 205089
* Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 ↵Craig Topper2014-02-051-4/+7
| | | | | | bools seemed excessive. llvm-svn: 200829
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+14
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-1/+1
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* Fixing a warning about control reaching the end of a non-void function.Aaron Ballman2013-08-161-0/+1
| | | | llvm-svn: 188524
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-47/+49
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src",Lang Hames2012-10-201-5/+6
| | | | | | rather than "$src = $dst"). llvm-svn: 166382
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-6/+5
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-12/+12
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson2012-09-111-1/+1
| | | | | | unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. llvm-svn: 163664
* Heed guessInstructionProperties, and stop warning on redundant flags.Jakob Stoklund Olesen2012-08-241-1/+2
| | | | | | | | | | | | Emit TableGen errors if guessInstructionProperties is 0 and instruction properties can't be inferred from patterns. Allow explicit instruction properties even when they can be inferred. This patch doesn't change the TableGen output. Redundant properties are not yet verified because the tree has errors. llvm-svn: 162516
* Tristate mayLoad, mayStore, and hasSideEffects.Jakob Stoklund Olesen2012-08-231-3/+6
| | | | | | | Keep track of the set/unset state of these bits along with their true/false values, but treat '?' as '0' for now. llvm-svn: 162461
* Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen2012-08-221-1/+1
| | | | | | | | | | | | | | | | | | | When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ llvm-svn: 162409
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-0/+1
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson2012-06-081-3/+25
| | | | | | complex operand are called out explicitly in the asm string. llvm-svn: 158183
* ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach2011-11-151-5/+12
| | | | | | rdar://10435076 llvm-svn: 144606
* Tidy up. Formatting.Jim Grosbach2011-11-151-1/+1
| | | | llvm-svn: 144598
* Allow InstAlias's to use immediate matcher patterns that xform the value.Jim Grosbach2011-10-281-2/+19
| | | | | | | | | For example, On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a matcher pattern that handles the bitwise negation when mapping to t2MVNi. llvm-svn: 143233
* Allow register classes to match a containing class in InstAliases.Jim Grosbach2011-10-281-0/+9
| | | | | | | | If the register class in the source alias is a subclass of the register class of the actual instruction, the alias can still match OK since the constraints are strictly a subset of what the instruction can actually handle. llvm-svn: 143200
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-2/+2
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-0/+1
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-1/+0
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* Follow up to r138791.Evan Cheng2011-08-301-0/+1
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Allow non zero_reg explicit values for OptionalDefOperands in aliases.Jim Grosbach2011-08-191-0/+7
| | | | llvm-svn: 138073
* Tidy up. Formatting.Jim Grosbach2011-08-191-2/+2
| | | | llvm-svn: 138067
* Unconstify InitsDavid Greene2011-07-291-18/+18
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
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