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| author | Andrew Trick <atrick@apple.com> | 2011-09-20 03:17:40 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-09-20 03:17:40 +0000 |
| commit | 8586e62d91771717510593cfedd0dfee226f9773 (patch) | |
| tree | 4c701b1e5f3eb731a1e3e999a8fdf7fa0a7988eb /llvm/utils/TableGen/CodeGenInstruction.cpp | |
| parent | 53df4b6dfa3300a98f9336f5fee7f676c878680d (diff) | |
| download | bcm5719-llvm-8586e62d91771717510593cfedd0dfee226f9773.tar.gz bcm5719-llvm-8586e62d91771717510593cfedd0dfee226f9773.zip | |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
Diffstat (limited to 'llvm/utils/TableGen/CodeGenInstruction.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenInstruction.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp index 4b252774f00..b4f9d150716 100644 --- a/llvm/utils/TableGen/CodeGenInstruction.cpp +++ b/llvm/utils/TableGen/CodeGenInstruction.cpp @@ -309,7 +309,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) { isReMaterializable = R->getValueAsBit("isReMaterializable"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); usesCustomInserter = R->getValueAsBit("usesCustomInserter"); - hasPostISelHook = R->getValueAsBit("hasPostISelHook"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); isNotDuplicable = R->getValueAsBit("isNotDuplicable"); hasSideEffects = R->getValueAsBit("hasSideEffects"); |
