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| author | Owen Anderson <resistor@mac.com> | 2015-05-28 18:33:39 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2015-05-28 18:33:39 +0000 |
| commit | abaa523e9ee3db49fabd2c58824d817ce1528293 (patch) | |
| tree | 1f59c629f718c28c691905c39d47185fa8bf3310 /llvm/utils/TableGen/CodeGenInstruction.cpp | |
| parent | adc06311babfb81a51c6cf0b98b38ca3df2889d0 (diff) | |
| download | bcm5719-llvm-abaa523e9ee3db49fabd2c58824d817ce1528293.tar.gz bcm5719-llvm-abaa523e9ee3db49fabd2c58824d817ce1528293.zip | |
Add support for the convergent flag at the MC and MachineInstr levels.
llvm-svn: 238450
Diffstat (limited to 'llvm/utils/TableGen/CodeGenInstruction.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenInstruction.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp index 10602964e48..8546a2ceaca 100644 --- a/llvm/utils/TableGen/CodeGenInstruction.cpp +++ b/llvm/utils/TableGen/CodeGenInstruction.cpp @@ -320,6 +320,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) isRegSequence = R->getValueAsBit("isRegSequence"); isExtractSubreg = R->getValueAsBit("isExtractSubreg"); isInsertSubreg = R->getValueAsBit("isInsertSubreg"); + isConvergent = R->getValueAsBit("isConvergent"); bool Unset; mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset); |
