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path: root/llvm/utils/TableGen/ARMDecoderEmitter.cpp
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* Remove the old-style ARM disassembler, which is no longer used.Owen Anderson2011-11-091-1790/+0
| | | | llvm-svn: 144243
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Unconstify InitsDavid Greene2011-07-291-10/+10
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-10/+10
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-2/+3
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-181-5/+0
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-181-7/+1
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-161-1/+7
| | | | llvm-svn: 135343
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-151-7/+1
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135319
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-11/+10
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-10/+11
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-061-0/+3
| | | | | | | | | | For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. llvm-svn: 134539
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-301-4/+0
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-301-2/+2
| | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-5/+1
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* ARM RSCS* don't need explicit TableGen decoder checks.Jim Grosbach2011-06-291-4/+0
| | | | | | | They've been pseudos for a while now, so the decoder will never see them in the first place. llvm-svn: 134101
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-291-3/+1
| | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. llvm-svn: 134092
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+5
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-2/+2
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+4
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+5
| | | | | | instructions, and add a test case for that. llvm-svn: 128249
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+5
| | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+4
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach2011-03-121-5/+0
| | | | llvm-svn: 127517
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-111-3/+0
| | | | llvm-svn: 127510
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-8/+0
| | | | llvm-svn: 127509
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-9/+0
| | | | llvm-svn: 127508
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-111-3/+2
| | | | llvm-svn: 127506
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-14/+0
| | | | llvm-svn: 127491
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-111-6/+0
| | | | | | as for VDUP32d and VDUP32q, respectively. llvm-svn: 127489
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-10/+0
| | | | llvm-svn: 127488
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-111-4/+1
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-111-7/+0
| | | | | | as for VREV64d32 and VREV64q32, respectively. llvm-svn: 127485
* Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach2011-03-111-6/+6
| | | | llvm-svn: 127445
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-101-4/+3
| | | | llvm-svn: 127434
* Memory barrier instructions don't need special handling in tblgen anymore.Jim Grosbach2011-03-101-3/+1
| | | | llvm-svn: 127419
* TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson2011-03-031-1/+1
| | | | llvm-svn: 126931
* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-1/+1
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
* Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson2011-02-181-96/+101
| | | | | | | | | | | | | fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. llvm-svn: 125966
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+4
| | | | | | instruction llvm-svn: 123770
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-8/+3
| | | | llvm-svn: 121798
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-131-5/+0
| | | | | | | | | | | | | Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. llvm-svn: 121730
* Merge DEBUG statements.Bill Wendling2010-12-131-8/+8
| | | | llvm-svn: 121660
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-3/+3
| | | | llvm-svn: 121659
* Remove reference to the CMPz instruction patterns for ARM.Jim Grosbach2010-12-071-8/+1
| | | | llvm-svn: 121180
* I did it wrong. Don't disregard these encodings here.Bill Wendling2010-12-031-7/+0
| | | | llvm-svn: 120786
* Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gprBill Wendling2010-12-031-0/+7
| | | | | | instructions. They are handled as special moves, but encoded as a normal move. llvm-svn: 120779
* The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,Jim Grosbach2010-11-301-5/+0
| | | | | | | no extra encoding information), so we no longer need to special case them here. llvm-svn: 120444
* Tidy up.Jim Grosbach2010-11-301-2/+3
| | | | llvm-svn: 120443
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