summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/ARMDecoderEmitter.cpp
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2011-03-12 01:05:29 +0000
committerJim Grosbach <grosbach@apple.com>2011-03-12 01:05:29 +0000
commitfcc34cacd95927f0c91c382ae6ebbf5ee6b6feab (patch)
treec45eadcad77062f611a24ba35f6e5106a8445189 /llvm/utils/TableGen/ARMDecoderEmitter.cpp
parent965fe994c2b7b000446b6ec574b6451687c7b34b (diff)
downloadbcm5719-llvm-fcc34cacd95927f0c91c382ae6ebbf5ee6b6feab.tar.gz
bcm5719-llvm-fcc34cacd95927f0c91c382ae6ebbf5ee6b6feab.zip
Remove no-longer-correct special case for disasm of ARM BL instructions.
llvm-svn: 127517
Diffstat (limited to 'llvm/utils/TableGen/ARMDecoderEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/ARMDecoderEmitter.cpp5
1 files changed, 0 insertions, 5 deletions
diff --git a/llvm/utils/TableGen/ARMDecoderEmitter.cpp b/llvm/utils/TableGen/ARMDecoderEmitter.cpp
index 2ebfb2e477b..09243e116b3 100644
--- a/llvm/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1592,11 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
- // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
- if (Name == "BL" || Name == "BL_pred" || Name == "BLX" ||
- Name == "BLX_pred" || Name == "TPsoft")
- return false;
-
// A8-598: VEXT
// Vector Extract extracts elements from the bottom end of the second
// operand vector and the top end of the first, concatenates them and
OpenPOWER on IntegriCloud