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* Fix DfaEmitter::visitDfaState() crash in MSVC x86 debug builds (PR44945)Hans Wennborg2020-02-252-5/+8
| | | | | | | No functionality change (intended), but this seems to make the code a bit clearer for the compiler and maybe for human readers too. (cherry picked from commit edae4be8e21c5deb9a8ffc24a8c17e70b878bf39)
* [X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1MFangrui Song2020-01-111-46/+42
| | | | | | | | | In x86Disassembler{OneByte,TwoByte,...}Codes, "/* EmptyTable */" is very common. Omitting it saves lots of space. Also, there is no need to display a table entry in multiple lines. It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}. Make use of zero-initialization.
* [AArch64] Add isAuthenticated predicate to MCInstDescVedant Kumar2020-01-104-0/+4
| | | | | | | | | | Add a predicate to MCInstDesc that allows tools to determine whether an instruction authenticates a pointer. This can be used by diagnostic tools to hint at pointer authentication failures. Differential Revision: https://reviews.llvm.org/D70329 rdar://55089604
* TableGen/GlobalISel: Fix pattern matching of immarg literalsMatt Arsenault2020-01-095-26/+65
| | | | | | | | | | | | | | | | | For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
* TableGen/GlobalISel: Add way for SDNodeXForm to work on timmMatt Arsenault2020-01-091-4/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation assumes there is an instruction associated with the transform, but this is not the case for timm/TargetConstant/immarg values. These transforms should directly operate on a specific MachineOperand in the source instruction. TableGen would assert if you attempted to define an equivalent GISDNodeXFormEquiv using timm when it failed to find the instruction matcher. Specially recognize SDNodeXForms on timm, and pass the operand index to the render function. Ideally this would be a separate render function type that looks like void renderFoo(MachineInstrBuilder, const MachineOperand&), but this proved to be somewhat mechanically painful. Add an optional operand index which will only be passed if the transform should only look at the one source operand. Theoretically it would also be possible to only ever pass the MachineOperand, and the existing renderers would check the parent. I think that would be somewhat ugly for the standard usage which may want to inspect other operands, and I also think MachineOperand should eventually not carry a pointer to the parent instruction. Use it in one sample pattern. This isn't a great example, since the transform exists to satisfy DAG type constraints. This could also be avoided by just changing the MachineInstr's arbitrary choice of operand type from i16 to i32. Other patterns have nontrivial uses, but this serves as the simplest example. One flaw this still has is if you try to use an SDNodeXForm defined for imm, but the source pattern uses timm, you still see the "Failed to lookup instruction" assert. However, there is now a way to avoid it.
* TableGen/GlobalISel: Address fixmeMatt Arsenault2020-01-091-5/+9
| | | | Don't call computeAvailableFunctionFeatures for every instruction.
* [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 ↵Eric Astor2020-01-092-41/+46
| | | | | | | | | | | | | | | | | | | assembly. Summary: Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions. Also add a regression test for llvm.org/PR44272, since this finishes fixing it. Reviewers: thakis, rnk Reviewed By: thakis Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72417
* TableGen: Remove unused codeMatt Arsenault2020-01-091-6/+0
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* TableGen/GlobalISel: Fix slightly wrong generated commentMatt Arsenault2020-01-091-1/+1
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* Fix warnings as errors that occur on sanitizer-x86_64-linuxDaniel Sanders2020-01-071-4/+4
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* Remove extraneous semicolon.Bill Wendling2020-01-071-1/+1
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* [gicombiner] Add GIMatchTree and use it for the code generationDaniel Sanders2020-01-0711-8/+1769
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GIMatchTree's job is to build a decision tree by zipping all the GIMatchDag's together. Each DAG is added to the tree builder as a leaf and partitioners are used to subdivide each node until there are no more partitioners to apply. At this point, the code generator is responsible for testing any untested predicates and following any unvisited traversals (there shouldn't be any of the latter as the getVRegDef partitioner handles them all). Note that the leaves don't always fit into partitions cleanly and the partitions may overlap as a result. This is resolved by cloning the leaf into every partition it belongs to. One example of this is a rule that can match one of N opcodes. The leaf for this rule would end up in N partitions when processed by the opcode partitioner. A similar example is the getVRegDef partitioner where having rules (add $a, $b), and (add ($a, $b), $c) will result in the former being in the partition for successfully following the vreg-def and failing to do so as it doesn't care which happens. Depends on D69151 Fixed the issues with the windows bots which were caused by stdout/stderr interleaving. Reviewers: bogner, volkan Reviewed By: volkan Subscribers: lkail, mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69152
* [MC] Add parameter `Address` to MCInstrPrinter::printInstructionFangrui Song2020-01-061-7/+8
| | | | | | | | Follow-up of D72172. Reviewed By: jhenderson, rnk Differential Revision: https://reviews.llvm.org/D72180
* TableGen/GlobalISel: Handle default operands that are usedMatt Arsenault2020-01-061-7/+37
| | | | | | | | | | Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
* [NFC] Fix trivial typos in commentsJames Henderson2020-01-062-4/+4
| | | | | | | | Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D72143 Patch by Kazuaki Ishizaki.
* Revert "[gicombiner] Add GIMatchTree and use it for the code generation"Daniel Sanders2020-01-0311-1769/+8
| | | | | | | | | All the windows bots are failing match-tree.td and there's no obvious cause that I can see. It's not just the %p formatting problem. My best guess is that there's an ordering issue too but I'll need further information to figure that out. Revert while I'm investigating. This reverts commit 64f1bb5cd2c6d69af7c74ec68840029603560238 and 77d4b5f5feff663e70b347516cc4c77fa5cd2a20
* [gicombiner] Add GIMatchTree and use it for the code generationDaniel Sanders2020-01-0311-8/+1769
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GIMatchTree's job is to build a decision tree by zipping all the GIMatchDag's together. Each DAG is added to the tree builder as a leaf and partitioners are used to subdivide each node until there are no more partitioners to apply. At this point, the code generator is responsible for testing any untested predicates and following any unvisited traversals (there shouldn't be any of the latter as the getVRegDef partitioner handles them all). Note that the leaves don't always fit into partitions cleanly and the partitions may overlap as a result. This is resolved by cloning the leaf into every partition it belongs to. One example of this is a rule that can match one of N opcodes. The leaf for this rule would end up in N partitions when processed by the opcode partitioner. A similar example is the getVRegDef partitioner where having rules (add $a, $b), and (add ($a, $b), $c) will result in the former being in the partition for successfully following the vreg-def and failing to do so as it doesn't care which happens. Depends on D69151 Reviewers: bogner, volkan Reviewed By: volkan Subscribers: lkail, mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69152
* [globalisel] Fix another mismatch between %d and the RuleID typeDaniel Sanders2020-01-031-1/+1
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* TableGen: Fix assert on PatFrags with predicate codeMatt Arsenault2019-12-301-5/+21
| | | | | | | | This assumed a single pattern if there was a predicate. Relax this a bit, and allow multiple patterns as long as they have the same class. This was only broken for the DAG path. GlobalISel seems to have handled this correctly already.
* [Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp}Fangrui Song2019-12-271-28/+0
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* [TableGen] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-225-10/+10
| | | | | | This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall. Differential Revision: https://reviews.llvm.org/D71807
* [globalisel] Small correction to the fixup in 0a0813962d6. The two ID's are ↵Daniel Sanders2019-12-181-2/+2
| | | | | | | not the same size The rule ID is a uint64_t as it has global scope but the UID is scoped to the rule and expected to be much smaller so it's only unsigned.
* [gicombiner] Import tryCombineIndexedLoadStore()Daniel Sanders2019-12-181-3/+4
| | | | | | | | | | | | | | | | | Summary: Now that arbitrary data is supported, import tryCombineIndexedLoadStore() Depends on D69147 Reviewers: bogner, volkan Reviewed By: volkan Subscribers: hiraditya, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69151
* [globalisel] Attempt to fix ARM bots that emit the correct number in the ↵Daniel Sanders2019-12-181-4/+5
| | | | wrong place
* [gicombiner] Add support for arbitrary match data being passed from match to ↵Daniel Sanders2019-12-181-0/+83
| | | | | | | | | | | | | | | | | | | | | apply Summary: This is used by the extending_loads combine to tell the apply step which use is the preferred one to fold and the other uses should be re-written to consume. Depends on D69117 Reviewers: volkan, bogner Reviewed By: volkan Subscribers: hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69147
* Revert "Temporarily Revert "[gicombiner] Add the MatchDag structure and ↵Daniel Sanders2019-12-1814-3/+1361
| | | | | | | | | | | | | | | | | | | parse instruction DAG's from the input"" This reverts commit e62e760f29567fe0841af870c65a4f8ef685d217. The issue @uweigand raised should have been fixed by iterating over the vector that owns the operand list data instead of the FoldingSet. The MSVC issue raised by @thakis should have been fixed by relaxing the regexes a little. I don't have a Windows machine available to test that so I tested it by using `perl -p -e 's/0x([0-9a-f]+)/\U\1\E/g' to convert the output of %p to the windows style. I've guessed at the issue @phosek raised as there wasn't enough information to investigate it. What I think is happening on that bot is the -debug option isn't available because the second stage build is a release build. I'm not sure why other release-mode bots didn't report it though.
* Temporarily Revert "[gicombiner] Add the MatchDag structure and parse ↵Eric Christopher2019-12-1714-1361/+3
| | | | | | | | | | | | instruction DAG's from the input" and follow-on patches. This is breaking a few build bots and local builds with follow-up already on the patch thread. This reverts commits 390c8baa5440dda8907688d9ef860f6982bd925f and 520e3d66e7257c77f1226185504bbe1cb90afcfa.
* [gicombiner] Process the MatchDag such that every node is reachable from the ↵Daniel Sanders2019-12-174-0/+93
| | | | | | | | | | | | | | | | | roots Summary: When we build the walk across these DAG's we need to be able to reach every node from the roots. Flip and traversal edges (so that use->def becomes def->uses) that make nodes unreachable. Note that early on we'll just error out on these flipped edges as def->uses edges are more complicated to match due to their one->many nature. Depends on D69077 Reviewers: volkan, bogner Subscribers: llvm-commits
* [gicombiner] Add the MatchDag structure and parse instruction DAG's from the ↵Daniel Sanders2019-12-1714-3/+1268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | input Summary: The MatchDag structure is a representation of the checks that need to be performed and the dependencies that limit when they can happen. There are two kinds of node in the MatchDag: * Instrs - Represent a MachineInstr * Predicates - Represent a check that needs to be performed (i.e. opcode, is register, same machine operand, etc.) and two kinds of edges: * (Traversal) Edges - Represent a register that can be traversed to find one instr from another * Predicate Dependency Edges - Indicate that a predicate requires a piece of information to be tested. For example, the matcher: (match (MOV $t, $s), (MOV $d, $t)) with MOV declared as an instruction of the form: %dst = MOV %src1 becomes the following MatchDag with the following instruction nodes: __anon0_0 // $t=getOperand(0), $s=getOperand(1) __anon0_1 // $d=getOperand(0), $t=getOperand(1) traversal edges: __anon0_1[src1] --[t]--> __anon0_0[dst] predicate nodes: <<$mi.getOpcode() == MOV>>:$__anonpred0_2 <<$mi.getOpcode() == MOV>>:$__anonpred0_3 and predicate dependencies: __anon0_0 ==> __anonpred0_2[mi] __anon0_0 ==> __anonpred0_3[mi] The result of this parse is currently unused but can be tested using -gicombiner-stop-after-parse as done in parse-match-pattern.td. The dump for testing includes a graphviz format dump to allow the rule to be viewed visually. Later on, these MatchDag's will be used to generate code and to build an efficient decision tree. Reviewers: volkan, bogner Reviewed By: volkan Subscribers: arsenm, mgorny, mgrang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69077
* [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes()Ana Pazos2019-12-161-69/+150
| | | | | | | | | | | | | | | | | | | Summary: Modified compression emitter tablegen backend to emit isCompressibleInst() check which in turn is used by getInstSizeInBytes() to better estimate instruction size. Note the generation of compressed instructions in RISC-V happens late in the assembler therefore instruction size estimate might be off if computed before. Reviewers: lenary, asb, luismarques, lewis-revill Reviewed By: asb Subscribers: sameer.abuasal, lewis-revill, hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68290
* [RISCV] Move DebugLoc Copy into CompressInstEmitterSam Elliott2019-12-131-0/+1
| | | | | | | | | | | | | | | | | | | | | Summary: This copy ensures that debug location information is kept for compressed instructions. There are places where both compressInstruction and uncompressInstruction are called that were not doing this copy, discarding some debug info. This change merely moves the copy into the generated file, so you cannot forget to copy the location over when compressing or uncompressing. Reviewers: asb, luismarques Reviewed By: luismarques Subscribers: sameer.abuasal, aprantl, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67493
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-11/+65
| | | | | | | | | | | | | | | | | | | | This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320
* [TableGen] Remove unused target intrinsic generation logicReid Kleckner2019-12-117-75/+20
| | | | | | | | | | | | AMDGPU was the last in tree target to use this tablegen mode. I plan to split up the global intrinsic enum similar to the way that clang diagnostics are split up today. I don't plan to build on this mode. Reviewers: arsenm, echristo, efriedma Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D71318
* [MC] Rewrite tablegen for printInstrAlias to comiple faster, NFCReid Kleckner2019-12-061-95/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the *InstPrinter.cpp files of each target where some of the slowest objects to compile in all of LLVM. See this snippet produced by ClangBuildAnalyzer: https://reviews.llvm.org/P8171$96 Search for "InstPrinter", and see that it shows up in a few places. Tablegen was emitting a large switch containing a sequence of operand checks, each of which created many conditions and many BBs. Register allocation and jump threading both did not scale well with such a large repetitive sequence of basic blocks. So, this change essentially turns those control flow structures into data. The previous structure looked like: switch (Opc) { case TGT::ADD: // check alias 1 if (MI->getOperandCount() == N && // check num opnds MI->getOperand(0).isReg() && // check opnd 0 ... MI->getOperand(1).isImm() && // check opnd 1 AsmString = "foo"; break; } // check alias 2 if (...) ... return false; The new structure looks like: OpToPatterns: Sorted table of opcodes mapping to pattern indices. \-> Patterns: List of patterns. Previous table points to subrange of patterns to match. \-> Conds: The if conditions above encoded as a kind and 32-bit value. See MCInstPrinter.cpp for the details of how the new data structures are interpreted. Here are some before and after metrics. Time to compile AArch64InstPrinter.cpp: 0m29.062s vs. 0m2.203s size of the obj: 3.9M vs. 676K size of clang.exe: 97M vs. 96M I have not benchmarked disassembly performance, but typically disassemblers are bottlenecked on IO and string processing, not alias matching, so I'm not sure it's interesting enough to be worth doing. Reviewers: RKSimon, andreadb, xbolva00, craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D70650
* Revert "Use InitLLVM to setup a pretty stack printer"Nico Weber2019-11-251-2/+2
| | | | | | | This reverts commit 3f76260dc0674cc0acb25f550a0f0c594cf537ea. Breaks at least these tests on Windows: Clang :: Driver/clang-offload-bundler.c Clang :: Driver/clang-offload-wrapper.c
* Use InitLLVM to setup a pretty stack printerRui Ueyama2019-11-261-2/+2
| | | | | | | | | | | | | | InitLLVM does not only save a few lines from main() but also makes the commands do the right thing for multibyte character pathnames on Windows (i.e. canonicalize argv's to UTF-8) because of the code we have in this file: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Support/InitLLVM.cpp#L32 For many LLVM commands, we already have calls of InitLLVM, but there are still remainings. Differential Revision: https://reviews.llvm.org/D70702
* [TableGen] Fixed 'unused but set variable' warning. NFCIDávid Bolvanský2019-11-241-2/+0
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* Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-231-0/+1
| | | | Fixed hashtable copy ctor.
* Revert 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-231-1/+0
| | | | pdbutil's test is failing.
* Fixed -Wdeprecated-copy warnings. NFCI.Dávid Bolvanský2019-11-231-0/+1
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* [TableGen] Add backend to generate command guide for tools using libOption.Jonas Devlieghere2019-11-227-72/+198
| | | | | | | | | | | | For lldb and dsymutil, the command guide is essentially a copy of its help output generated by libOption. Making sure the two stay in sync is tedious and error prone. Given that we already generate the help from a tablegen file, we might as well generate the RST as well. This adds a tablegen backend for generating Sphinx/RST command guides from the tablegen file. Differential revision: https://reviews.llvm.org/D70610
* [PGO][PGSO] DAG.shouldOptForSize part.Hiroshi Yamauchi2019-11-211-0/+8
| | | | | | | | | | | | | | | Summary: (Split of off D67120) SelectionDAG::shouldOptForSize changes for profile guided size optimization. Reviewers: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70095
* [SVE][CodeGen] Scalable vector MVT size queriesGraham Hunter2019-11-181-12/+23
| | | | | | | | | | | | | | | | | | | * Implements scalable size queries for MVTs, split out from D53137. * Contains a fix for FindMemType to avoid using scalable vector type to contain non-scalable types. * Explicit casts for several places where implicit integer sign changes or promotion from 32 to 64 bits caused problems. * CodeGenDAGPatterns will treat scalable and non-scalable vector types as different. Reviewers: greened, cameron.mcinally, sdesmalen, rovka Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D66871
* CodeGenRegBank - make functions const to fix cppcheck warnings.Simon Pilgrim2019-11-101-3/+5
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* Reduce scope of variable to silence cppcheck warning. NFCSimon Pilgrim2019-11-091-2/+1
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* Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-091-2/+2
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* AsmWriterOperand - fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-071-1/+1
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* TableGen: Remove assert that pattern results match input numberMatt Arsenault2019-11-061-1/+0
| | | | | | | AMDGPU has some atomic instructions that do not return the previous result, and can only be selected if there are no uses. The source pattern will only match if the use is empty, so it should be safe to discard the result.
* CodeGenInstruction - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-061-5/+6
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* X86FoldTablesEmitter - fix static analyzer potential invalid iterator ↵Simon Pilgrim2019-11-061-3/+3
| | | | warning. NFCI.
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