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| author | Jim Grosbach <grosbach@apple.com> | 2011-06-29 22:01:15 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-06-29 22:01:15 +0000 |
| commit | 1c2d4f2feaf680df14b0a6a2f23e2d96589ac598 (patch) | |
| tree | aa20341eff51c7ecb30b796e791dd09ae45c1cec /llvm/utils/TableGen/ARMDecoderEmitter.cpp | |
| parent | 77ec04c656364965d1100eee6576a506a5f3c341 (diff) | |
| download | bcm5719-llvm-1c2d4f2feaf680df14b0a6a2f23e2d96589ac598.tar.gz bcm5719-llvm-1c2d4f2feaf680df14b0a6a2f23e2d96589ac598.zip | |
ARM RSCS* don't need explicit TableGen decoder checks.
They've been pseudos for a while now, so the decoder will never see
them in the first place.
llvm-svn: 134101
Diffstat (limited to 'llvm/utils/TableGen/ARMDecoderEmitter.cpp')
| -rw-r--r-- | llvm/utils/TableGen/ARMDecoderEmitter.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/utils/TableGen/ARMDecoderEmitter.cpp b/llvm/utils/TableGen/ARMDecoderEmitter.cpp index cccfefde703..a320e77b287 100644 --- a/llvm/utils/TableGen/ARMDecoderEmitter.cpp +++ b/llvm/utils/TableGen/ARMDecoderEmitter.cpp @@ -1592,10 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, // The following special cases are for conflict resolutions. // - // RSCSri and RSCSrs set the 's' bit, but are not predicated. We are - // better off using the generic RSCri and RSCrs instructions. - if (Name == "RSCSri" || Name == "RSCSrs") return false; - // A8-598: VEXT // Vector Extract extracts elements from the bottom end of the second // operand vector and the top end of the first, concatenates them and |
