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* [X86] Teach Intel syntax InstPrinter to print lock prefixes that have been ↵Craig Topper2018-01-251-0/+6
| | | | | | | | parsed from the asm parser. The asm parser puts the lock prefix in the MCInst flags so we need to check that in addition to TSFlags. This matches what the ATT printer does. llvm-svn: 323469
* Revert r322132; it appears to be an accidental commit, based on the commit ↵Aaron Ballman2018-01-251-27/+0
| | | | | | message. The original author of the commit has not commented on whether this was accidental or purposeful, so if this revert is in error, the author can re-commit with an actual commit message. llvm-svn: 323466
* Reverting r323463 as it appears to be an accidental commit. Regardless, it ↵Aaron Ballman2018-01-253-3/+1
| | | | | | | | | | broke a lot of build bots, so reverting back to green. http://lab.llvm.org:8011/builders/lldb-amd64-ninja-netbsd8/builds/9294 http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/24084 http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/9567 llvm-svn: 323465
* tmpJake Ehrlich2018-01-253-1/+3
| | | | llvm-svn: 323463
* Revert "asan: add kernel inline instrumentation test"Vedant Kumar2018-01-251-27/+0
| | | | | | | | This reverts commit r323451. It breaks this bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/24077 llvm-svn: 323454
* [Hexagon] SETEQ and SETNE are valid integer condition codesKrzysztof Parzyszek2018-01-251-0/+21
| | | | llvm-svn: 323452
* asan: add kernel inline instrumentation testVedant Kumar2018-01-251-0/+27
| | | | | | | | Patch by Andrey Konovalov! Differential Revision: https://reviews.llvm.org/D42473 llvm-svn: 323451
* Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements ↵Alexey Bataev2018-01-253-24/+24
| | | | | | | | as shuffle." This reverts commit r323441 to fix buildbots. llvm-svn: 323447
* [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.Alexey Bataev2018-01-253-24/+24
| | | | | | | | | | | | | | | | | Summary: If the same value is going to be vectorized several times in the same tree entry, this entry is considered to be a gather entry and cost of this gather is counter as cost of InsertElementInstrs for each gathered value. But we can consider these elements as ShuffleInstr with SK_PermuteSingle shuffle kind. Reviewers: spatel, RKSimon, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38697 llvm-svn: 323441
* [InstCombine] narrow masked zexted binops (PR35792)Sanjay Patel2018-01-251-48/+84
| | | | | | | | | | | | | | | | | This is guarded by shouldChangeType(), so the tests show that we don't do the fold if the narrower type is not legal. Note that there is a proposal (D42424) that would change the results for the specific cases shown in these tests. That difference is also discussed in PR35792: https://bugs.llvm.org/show_bug.cgi?id=35792 Alive proofs for the cases handled here as well as the bitwise logic binops that we should already do better on: https://rise4fun.com/Alive/c97 https://rise4fun.com/Alive/Lc5E https://rise4fun.com/Alive/kdf llvm-svn: 323437
* [InstCombine] add tests for PR35792; NFCSanjay Patel2018-01-251-0/+192
| | | | llvm-svn: 323436
* Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements ↵Alexey Bataev2018-01-253-24/+24
| | | | | | | | as shuffle." This reverts commit r323430 to fix buildbots. llvm-svn: 323432
* [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.Alexey Bataev2018-01-253-24/+24
| | | | | | | | | | | | | | | | | Summary: If the same value is going to be vectorized several times in the same tree entry, this entry is considered to be a gather entry and cost of this gather is counter as cost of InsertElementInstrs for each gathered value. But we can consider these elements as ShuffleInstr with SK_PermuteSingle shuffle kind. Reviewers: spatel, RKSimon, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38697 llvm-svn: 323430
* [X86][SSE] Add tests for vector truncation with signed saturationSimon Pilgrim2018-01-251-0/+3520
| | | | | | AVX512 isn't using X86ISD::VTRUNCS and SSE/AVX isn't using PACKSS/PACKUS llvm-svn: 323428
* [X86][SSE] Add tests for vector truncation with unsigned saturationSimon Pilgrim2018-01-251-0/+2352
| | | | | | AVX512 tends to do a good job, but there are some missed opportunities with SSE/AVX llvm-svn: 323422
* X86 Tests: Add AVX+XOP config to SDIV combine testsZvi Rackover2018-01-251-0/+622
| | | | | | | As pointed out in D42479, XOP also needs to be covered as it supports vector shifts with variable shift amount. llvm-svn: 323418
* Another try to commit 323321 (aggressive instruction combine).Amjad Aboud2018-01-255-2/+299
| | | | llvm-svn: 323416
* [GlobalOpt] Emit fragments using field offsets from struct layoutMikael Holmen2018-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: When creating the debug fragments for a SRA'd struct, use the fields' offsets, taken from the struct layout, as the offsets for the resulting fragments. This fixes an issue where GlobalOpt would emit fragments with incorrect offsets for padded fields. This should solve PR36016. Patch by David Stenberg. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42489 llvm-svn: 323411
* [IRMover] Add comment and fix test caseEugene Leviant2018-01-251-1/+5
| | | | llvm-svn: 323407
* [X86] Expand IMUL/MUL instregexs in Intel scheduler models. Add load latency ↵Craig Topper2018-01-251-29/+29
| | | | | | | | | | | | to some of them in SkylakeClient model. The regular expressions and the imul names caused some instructions to be matched by multiple regexs creating unpredictable results. This changes them all to use explicit instrs instead. While doing this I also found that some instructions in Skylake were missing load latency so I fixed that too. llvm-svn: 323406
* [X86] Remove 64/128/256 from MMX/SSE/AVX instruction names for overall ↵Craig Topper2018-01-251-1/+1
| | | | | | | | | | consistency. NFC MMX instrutions all start with MMX_ so the 64 isn't needed for disambigutation. SSE/AVX1 instructions are assumed 128-bit so we don't need to say 128. AVX2 instructions should use a Y to indicate 256-bits. llvm-svn: 323402
* [GlobalISel] Add a requires: asserts to a test.Amara Emerson2018-01-241-0/+1
| | | | llvm-svn: 323384
* [InstCombine] fix datalayout in test fileSanjay Patel2018-01-241-1/+1
| | | | | | | | | | | | | | The only part of the datalayout that should matter for these tests is the part that specifies the legal int widths ('n*'). But there was a bug - that part of the string was not correctly separated with the expected '-' character, so we were testing as if there were no legal int widths at all. Removed the leading cruft so we have some legal ints to test with. I noticed this while testing a potential change to the way we transform shifts and sexts in D42424. llvm-svn: 323377
* [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load.Amara Emerson2018-01-241-0/+14
| | | | | | | | | | | | | | | The tablegen imported patterns for sext(load(a)) don't check for single uses of the load or delete the original after matching. As a result two loads are left in the generated code. This particular issue will be fixed by adding support for a G_SEXTLOAD opcode in future. There are however other potential issues around this that wouldn't be fixed by a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile loads at all in the AArch64 selector. Fixes/works around PR36018. llvm-svn: 323371
* [GlobalISel] Don't fall back to FastISel.Amara Emerson2018-01-241-0/+10
| | | | | | | Apparently checking the pass structure isn't enough to ensure that we don't fall back to FastISel, as it's set up as part of the SelectionDAGISel. llvm-svn: 323369
* [X86][SSE] Aggressively use PMADDWD for v4i32 multiplies with 17 or more ↵Simon Pilgrim2018-01-243-170/+374
| | | | | | | | | | | | leading zeros As discussed in D41484, PMADDWD for 'zero extended' vXi32 is nearly always a better option than PMULLD: On SNB it will result in code that isn't any faster, but not any slower so we may as well keep it. On KNL it only has half the throughput, so I've disabled it on there - ideally there'd be a better way than this. Differential Revision: https://reviews.llvm.org/D42258 llvm-svn: 323367
* [X86][SSE] Add slow-pmulld attribute (silvermont-style) testSimon Pilgrim2018-01-241-247/+505
| | | | | | Requested by @zvi on D42258 llvm-svn: 323364
* Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements ↵Alexey Bataev2018-01-243-24/+24
| | | | | | | | as shuffle." This reverts commit r323348 because of the broken buildbots. llvm-svn: 323359
* Revert "[ThinLTO] Add call edges' relative block frequency to per-module ↵Easwaran Raman2018-01-241-35/+0
| | | | | | | | summary." Causes buildbot regressions. llvm-svn: 323358
* Revert r321751, "StructurizeCFG: Fix broken backedge detection"Nicolai Haehnle2018-01-245-144/+123
| | | | | | | | | | | It causes regressions in various OpenGL test suites. Keep the test cases introduced by r321751 as XFAIL, and add a test case for the regression. Change-Id: I90b4cc354f68cebe5fcef1f2422dc8fe1c6d3514 Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36015 llvm-svn: 323355
* [ARM] Expand long shifts for Thumb1 to __aeabi_ callsWeiming Zhao2018-01-241-0/+15
| | | | | | | | | | | | | | Summary: For long shifts, the inlined version takes about 20 instructions on Thumb1. To avoid the code bloat, expand to __aeabi_ calls if target is Thumb1. Reviewers: samparker Reviewed By: samparker Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42401 llvm-svn: 323354
* [X86] Fix some inconsistencies in the itineraries and Sched for ↵Craig Topper2018-01-242-2/+2
| | | | | | | | (V)PEXTRW/(V)PINSRW The weirdest being that PEXTRWrr was tagged as a memory operation. llvm-svn: 323353
* [X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 ↵Craig Topper2018-01-242-5/+5
| | | | | | for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI llvm-svn: 323352
* [ThinLTO] Add call edges' relative block frequency to per-module summary.Easwaran Raman2018-01-241-0/+35
| | | | | | | | | | | | | | | Summary: This allows relative block frequency of call edges to be passed to the thinlink stage where it will be used to compute synthetic entry counts of functions. Reviewers: tejohnson, pcc Subscribers: mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D42212 llvm-svn: 323349
* [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.Alexey Bataev2018-01-243-24/+24
| | | | | | | | | | | | | | | | | Summary: If the same value is going to be vectorized several times in the same tree entry, this entry is considered to be a gather entry and cost of this gather is counter as cost of InsertElementInstrs for each gathered value. But we can consider these elements as ShuffleInstr with SK_PermuteSingle shuffle kind. Reviewers: spatel, RKSimon, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38697 llvm-svn: 323348
* [Hexagon] Run late copy propagation and dead code elimination passesKrzysztof Parzyszek2018-01-2410-37/+43
| | | | llvm-svn: 323346
* InstSimplify: If divisor element is undef simplify to undefZvi Rackover2018-01-242-0/+32
| | | | | | | | | | | | | | | | Summary: If any vector divisor element is undef, we can arbitrarily choose it be zero which would make the div/rem an undef value by definition. Reviewers: spatel, reames Reviewed By: spatel Subscribers: magabari, llvm-commits Differential Revision: https://reviews.llvm.org/D42485 llvm-svn: 323343
* [ValueTracking] add recursion depth param to matchSelectPattern Sanjay Patel2018-01-241-0/+46
| | | | | | | | | | | | | | | | | | | | | | | We're getting bug reports: https://bugs.llvm.org/show_bug.cgi?id=35807 https://bugs.llvm.org/show_bug.cgi?id=35840 https://bugs.llvm.org/show_bug.cgi?id=36045 ...where we blow up the stack in value tracking because other passes are sending in selects that have an operand that is itself the select. We don't currently have a reliable way to avoid analyzing dead code that may take non-standard forms, so bail out when things go too far. This mimics the recursion depth limitations in other parts of value tracking. Unfortunately, this pushes the underlying problems for other passes (jump-threading, simplifycfg, correlated-propagation) into hiding. If someone wants to uncover those again, the first draft of this patch on Phab would do that (it would assert rather than bail out). Differential Revision: https://reviews.llvm.org/D42442 llvm-svn: 323331
* X86 Tests: Add more sdiv combine cases. NFCZvi Rackover2018-01-241-9/+3160
| | | | | | Add cases with vector non-splat pow2 contant divider. llvm-svn: 323329
* Regenerate shuffle sink testSimon Pilgrim2018-01-241-28/+39
| | | | llvm-svn: 323328
* Reverted 323321.Amjad Aboud2018-01-244-220/+2
| | | | llvm-svn: 323326
* [AArch64] Avoid unnecessary vector byte-swapping in big-endianPablo Barrio2018-01-241-55/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Loads/stores of some NEON vector types are promoted to other vector types with different lane sizes but same vector size. This is not a problem in little-endian but, when in big-endian, it requires additional byte reversals required to preserve the lane ordering while keeping the right endianness of the data inside each lane. For example: %1 = load <4 x half>, <4 x half>* %p results in the following assembly: ld1 { v0.2s }, [x1] rev32 v0.4h, v0.4h This patch changes the promotion of these loads/stores so that the actual vector load/store (LD1/ST1) takes care of the endianness correctly and there is no need for further byte reversals. The previous code now results in the following assembly: ld1 { v0.4h }, [x1] Reviewers: olista01, SjoerdMeijer, efriedma Reviewed By: efriedma Subscribers: aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D42235 llvm-svn: 323325
* [DebugInfo] Emit DWARF reference for DIVariable 'count' in DISubrangeSander de Smalen2018-01-241-0/+50
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements the codegen of DWARF debug info for non-constant 'count' fields for DISubrange. This is patch [2/3] in a series to extend LLVM's DISubrange Metadata node to support debugging of C99 variable length arrays and vectors with runtime length like the Scalable Vector Extension for AArch64. It is also a first step towards representing more complex cases like arrays in Fortran. Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie Reviewed By: aprantl Subscribers: fhahn, aemerson, rengolin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41696 llvm-svn: 323323
* [InstCombine] Introducing Aggressive Instruction Combine pass ↵Amjad Aboud2018-01-244-2/+220
| | | | | | | | | | | | | | | | | | (-aggressive-instcombine). Combine expression patterns to form expressions with fewer, simple instructions. This pass does not modify the CFG. For example, this pass reduce width of expressions post-dominated by TruncInst into smaller width when applicable. It differs from instcombine pass in that it contains pattern optimization that requires higher complexity than the O(1), thus, it should run fewer times than instcombine pass. Differential Revision: https://reviews.llvm.org/D38313 llvm-svn: 323321
* [Metadata] Extend 'count' field of DISubrange to take a metadata nodeSander de Smalen2018-01-245-0/+131
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch extends the DISubrange 'count' field to take either a (signed) constant integer value or a reference to a DILocalVariable or DIGlobalVariable. This is patch [1/3] in a series to extend LLVM's DISubrange Metadata node to support debugging of C99 variable length arrays and vectors with runtime length like the Scalable Vector Extension for AArch64. It is also a first step towards representing more complex cases like arrays in Fortran. Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie Reviewed By: aprantl Subscribers: rnk, probinson, fhahn, aemerson, rengolin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41695 llvm-svn: 323313
* [DAGCombiner] Bail out if vector size is not a multipleSven van Haastregt2018-01-241-0/+12
| | | | | | | | | | | | For the included test case, the DAG transformation concat_vectors(scalar, undef) -> scalar_to_vector(sclr) would attempt to create a v2i32 vector for a v9i8 concat_vector. Bail out to avoid creating a bitcast with mismatching sizes later on. Differential Revision: https://reviews.llvm.org/D42379 llvm-svn: 323312
* [NFC] Remove overconfident assert from IRCEMax Kazantsev2018-01-241-0/+42
| | | | | | | | | This patch removes assert that SCEV is able to prove that a value is non-negative. In fact, SCEV can sometimes be unable to do this because its cache does not update properly. This assert will be returned once this problem is resolved. llvm-svn: 323309
* [ARM] Call __chkstk for dynamic stack allocation in all windows environmentsMartin Storsjo2018-01-242-4/+3
| | | | | | | | | | | | | | | This matches what MSVC does for alloca() function calls on ARM. Even if MSVC doesn't support VLAs at the language level, it does support the alloca function. On the clang level, both the _alloca() (when emulating MSVC, which is what the alloca() function expands to) and __builtin_alloca() builtin functions, and VLAs, map to the same LLVM IR "alloca" function - so within LLVM they're not distinguishable from each other. Differential Revision: https://reviews.llvm.org/D42292 llvm-svn: 323308
* [GlobalMerge] Don't merge dllexport globalsMartin Storsjo2018-01-242-0/+30
| | | | | | | | | Merging such globals loses the dllexport attribute. Add a test to check that normal globals still are merged. Differential Revision: https://reviews.llvm.org/D42127 llvm-svn: 323307
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-245-6/+6
| | | | | | "the the" -> "the" llvm-svn: 323302
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