[InstCombine] add tests for PR35792; NFC

llvm-svn: 323436

1 files changed, 192 insertions, 0 deletions

diff --git a/llvm/test/Transforms/InstCombine/and-narrow.ll b/llvm/test/Transforms/InstCombine/and-narrow.ll
new file mode 100644
index 00000000000..f5d96b1dc4d
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/and-narrow.ll
@@ -0,0 +1,192 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -data-layout="n8:16:32" -S | FileCheck %s --check-prefix=ALL --check-prefix=LEGAL8
+; RUN: opt < %s -instcombine -data-layout="n16"      -S | FileCheck %s --check-prefix=ALL --check-prefix=LEGAL16
+
+; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=35792
+
+define i16 @zext_add(i8 %x) {
+; ALL-LABEL: @zext_add(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[B:%.*]] = add nuw nsw i16 [[Z]], 44
+; ALL-NEXT:    [[R:%.*]] = and i16 [[B]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = add i16 %z, 44
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define i16 @zext_sub(i8 %x) {
+; ALL-LABEL: @zext_sub(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[B:%.*]] = sub nsw i16 251, [[Z]]
+; ALL-NEXT:    [[R:%.*]] = and i16 [[B]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = sub i16 -5, %z
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define i16 @zext_mul(i8 %x) {
+; ALL-LABEL: @zext_mul(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[B:%.*]] = mul nuw nsw i16 [[Z]], 3
+; ALL-NEXT:    [[R:%.*]] = and i16 [[B]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = mul i16 %z, 3
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define i16 @zext_lshr(i8 %x) {
+; ALL-LABEL: @zext_lshr(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[B:%.*]] = lshr i16 [[Z]], 4
+; ALL-NEXT:    [[R:%.*]] = and i16 [[B]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = lshr i16 %z, 4
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define i16 @zext_ashr(i8 %x) {
+; ALL-LABEL: @zext_ashr(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[TMP1:%.*]] = lshr i16 [[Z]], 2
+; ALL-NEXT:    [[R:%.*]] = and i16 [[TMP1]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = ashr i16 %z, 2
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define i16 @zext_shl(i8 %x) {
+; ALL-LABEL: @zext_shl(
+; ALL-NEXT:    [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; ALL-NEXT:    [[B:%.*]] = shl nuw nsw i16 [[Z]], 3
+; ALL-NEXT:    [[R:%.*]] = and i16 [[B]], [[Z]]
+; ALL-NEXT:    ret i16 [[R]]
+;
+  %z = zext i8 %x to i16
+  %b = shl i16 %z, 3
+  %r = and i16 %b, %z
+  ret i16 %r
+}
+
+define <2 x i16> @zext_add_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_add_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = add nuw nsw <2 x i16> [[Z]], <i16 44, i16 42>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = add <2 x i16> %z, <i16 44, i16 42>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+define <2 x i16> @zext_sub_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_sub_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = sub nuw nsw <2 x i16> <i16 -5, i16 -4>, [[Z]]
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = sub <2 x i16> <i16 -5, i16 -4>, %z
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+define <2 x i16> @zext_mul_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_mul_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = mul nsw <2 x i16> [[Z]], <i16 3, i16 -2>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = mul <2 x i16> %z, <i16 3, i16 -2>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+define <2 x i16> @zext_lshr_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_lshr_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 4, i16 2>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = lshr <2 x i16> %z, <i16 4, i16 2>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+define <2 x i16> @zext_ashr_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_ashr_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 2, i16 3>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = ashr <2 x i16> %z, <i16 2, i16 3>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+define <2 x i16> @zext_shl_vec(<2 x i8> %x) {
+; ALL-LABEL: @zext_shl_vec(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = shl <2 x i16> [[Z]], <i16 3, i16 2>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = shl <2 x i16> %z, <i16 3, i16 2>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+; Don't create poison by narrowing a shift below the shift amount.
+
+define <2 x i16> @zext_lshr_vec_overshift(<2 x i8> %x) {
+; ALL-LABEL: @zext_lshr_vec_overshift(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 4, i16 8>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = lshr <2 x i16> %z, <i16 4, i16 8>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+
+; Don't create poison by narrowing a shift below the shift amount.
+
+define <2 x i16> @zext_shl_vec_overshift(<2 x i8> %x) {
+; ALL-LABEL: @zext_shl_vec_overshift(
+; ALL-NEXT:    [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; ALL-NEXT:    [[B:%.*]] = shl <2 x i16> [[Z]], <i16 8, i16 2>
+; ALL-NEXT:    [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
+; ALL-NEXT:    ret <2 x i16> [[R]]
+;
+  %z = zext <2 x i8> %x to <2 x i16>
+  %b = shl <2 x i16> %z, <i16 8, i16 2>
+  %r = and <2 x i16> %b, %z
+  ret <2 x i16> %r
+}
+