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| author | Craig Topper <craig.topper@intel.com> | 2018-01-24 17:58:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-24 17:58:51 +0000 |
| commit | b85b484feed6eae184890dbd4f8c1986aaf62c17 (patch) | |
| tree | 76576ca5a3c6b13dfeba40cf07299782a4c5a648 /llvm/test | |
| parent | 23cc866c97e7e20941c48c9e803c31ef3dbdc874 (diff) | |
| download | bcm5719-llvm-b85b484feed6eae184890dbd4f8c1986aaf62c17.tar.gz bcm5719-llvm-b85b484feed6eae184890dbd4f8c1986aaf62c17.zip | |
[X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI
llvm-svn: 323352
Diffstat (limited to 'llvm/test')
| -rwxr-xr-x | llvm/test/CodeGen/X86/evex-to-vex-compress.mir | 6 | ||||
| -rw-r--r-- | llvm/test/MC/X86/x86_64-asm-match.s | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir index 8f4c050719a..5b593b3e84a 100755 --- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir +++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir @@ -2088,7 +2088,7 @@ body: | %rax = VPEXTRQZrr %xmm0, 1 ; CHECK: VPEXTRWmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3 VPEXTRWZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3 - ; CHECK: %eax = VPEXTRWri %xmm0, 1 + ; CHECK: %eax = VPEXTRWrr %xmm0, 1 %eax = VPEXTRWZrr %xmm0, 1 ; CHECK: %eax = VPEXTRWrr_REV %xmm0, 1 %eax = VPEXTRWZrr_REV %xmm0, 1 @@ -2104,9 +2104,9 @@ body: | %xmm0 = VPINSRQZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3 ; CHECK: %xmm0 = VPINSRQrr %xmm0, %rdi, 5 %xmm0 = VPINSRQZrr %xmm0, %rdi, 5 - ; CHECK: %xmm0 = VPINSRWrmi %xmm0, %rsi, 1, %noreg, 0, %noreg, 3 + ; CHECK: %xmm0 = VPINSRWrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3 %xmm0 = VPINSRWZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3 - ; CHECK: %xmm0 = VPINSRWrri %xmm0, %edi, 5 + ; CHECK: %xmm0 = VPINSRWrr %xmm0, %edi, 5 %xmm0 = VPINSRWZrr %xmm0, %edi, 5 ; CHECK: %xmm0 = VSQRTSDm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg %xmm0 = VSQRTSDZm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s index 5cc31fc8077..fb7f7dadf91 100644 --- a/llvm/test/MC/X86/x86_64-asm-match.s +++ b/llvm/test/MC/X86/x86_64-asm-match.s @@ -17,11 +17,11 @@ // CHECK: Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:xmm2): match success using generic matcher // CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode // CHECK: AsmMatcher: found 4 encodings with mnemonic 'pinsrw' -// CHECK: Trying to match opcode MMX_PINSRWirri +// CHECK: Trying to match opcode MMX_PINSRWrr // CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher // CHECK: Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher // CHECK: Matching formal operand class MCK_VR64 against actual operand at index 3 (Reg:xmm5): Opcode result: multiple operand mismatches, ignoring this opcode -// CHECK: Trying to match opcode PINSRWrri +// CHECK: Trying to match opcode PINSRWrr // CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher // CHECK: Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher // CHECK: Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:xmm5): match success using generic matcher |
