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authorSven van Haastregt <sven.vanhaastregt@arm.com>2018-01-24 09:53:47 +0000
committerSven van Haastregt <sven.vanhaastregt@arm.com>2018-01-24 09:53:47 +0000
commite8404780c38e44ccbbc1cd89873929ed4c49dac0 (patch)
tree09198fe18b1afe20c797e25e0741ac80e654deaa /llvm/test
parent83a561584d28831a62da203cda532fe8da9cd295 (diff)
downloadbcm5719-llvm-e8404780c38e44ccbbc1cd89873929ed4c49dac0.tar.gz
bcm5719-llvm-e8404780c38e44ccbbc1cd89873929ed4c49dac0.zip
[DAGCombiner] Bail out if vector size is not a multiple
For the included test case, the DAG transformation concat_vectors(scalar, undef) -> scalar_to_vector(sclr) would attempt to create a v2i32 vector for a v9i8 concat_vector. Bail out to avoid creating a bitcast with mismatching sizes later on. Differential Revision: https://reviews.llvm.org/D42379 llvm-svn: 323312
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AMDGPU/concat_vectors.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll
index 7394842d156..e8d98ba8935 100644
--- a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll
+++ b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll
@@ -294,3 +294,15 @@ bb:
store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
ret void
}
+
+; FUNC-LABEL: {{^}}concat_vector_crash2:
+; SI: s_endpgm
+define amdgpu_kernel void @concat_vector_crash2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) {
+ %tmp = load i32, i32 addrspace(1)* %in, align 1
+ %tmp1 = trunc i32 %tmp to i24
+ %tmp2 = bitcast i24 %tmp1 to <3 x i8>
+ %tmp3 = shufflevector <3 x i8> %tmp2, <3 x i8> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef>
+ %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 7, i8 8>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
+ store <8 x i8> %tmp4, <8 x i8> addrspace(1)* %out, align 8
+ ret void
+}
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