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* [mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructionsSimon Atanasyan2019-10-031-0/+10
| | | | llvm-svn: 373591
* [mips] Support sigrie instructionSimon Atanasyan2018-11-061-0/+4
| | | | | | | | | The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
* [mips] Add missing instructionsAleksandar Beserminji2018-08-291-3/+0
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-011-14/+0
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-141-0/+12
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [mips] Accept 32-bit offsets for ld/sd/lld commandsSimon Atanasyan2018-05-101-6/+6
| | | | | | | | | | | | This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
* [mips] Accept 32-bit offsets for lh and lhu commandsSimon Atanasyan2018-05-101-4/+4
| | | | | | | | | | This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-041-4/+8
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-021-8/+4
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-021-4/+8
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-021-3/+45
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-251-1/+4
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* [mips] Show an error if register number is out of rangeSimon Atanasyan2018-04-241-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
* [mips] Correct the predicates of the load/store (double)word for coprocessor 3.Simon Dardis2018-04-121-0/+2
| | | | llvm-svn: 329913
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-121-1/+20
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* Revert "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-03-131-27/+3
| | | | | | | | | This appears to have broken the expensive checks bot in a strange fashion. Reverting until I can investigate. This reverts r327409. llvm-svn: 327427
* [mips] Guard traps for microMIPS correctlySimon Dardis2018-03-131-3/+27
| | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 llvm-svn: 327409
* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-203-14/+14
| | | | | | | | | | | This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-183-14/+14
| | | | | | | | | | This reverts changes r320992, r320986, r320973, and r320970. r320970 by itself breaks the test case, and the rest depend on it. Test case will land soon. llvm-svn: 321024
* [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ↵Sander de Smalen2017-12-183-14/+14
| | | | | | | | | | | | | | | | | | | | | | | instruction Summary: When emitting a diagnostic for an invalid operand, a specific diagnostic should only be reported when the instruction being matched is actually enabled by the feature flags. Patch [3/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund Reviewed By: olista01, sdardis Subscribers: fhahn, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40362 llvm-svn: 320986
* [mips] Add test cases for dext/dins family of instructionsAleksandar Beserminji2017-09-292-0/+30
| | | | | | | | | Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 llvm-svn: 314503
* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-141-0/+4
| | | | | | | | | | | | | | | | The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
* [mips] correct operand range for DINSM instructionPetar Jovanovic2017-09-131-0/+1
| | | | | | | | | | | | | This patch corrects the definition of the DINSM instruction. Specification for DINSM instruction for Mips64 says that size operand should be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives range of 1 .. 32. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D37683 llvm-svn: 313149
* [mips][microMIPS] add lapc instructionPetar Jovanovic2017-09-113-4/+14
| | | | | | | | | | Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
* [mips] Add instruction aliases for ds(r|l)l.Simon Dardis2017-06-271-3/+7
| | | | | | | Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
* Reland r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-231-2/+2
| | | | | | | | | | | | | | | | After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
* Revert r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-231-2/+2
| | | | | | | | | | | | | | | ELF/mips-plt-r6.s in lld-test is failing. Reverting the change. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306099
* [mips] Fix register positions in the aui/daui instructionsPetar Jovanovic2017-06-231-2/+2
| | | | | | | | | | | | Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D33988 llvm-svn: 306095
* [mips] seb, seh instruction aliasesSimon Dardis2016-11-221-0/+4
| | | | | | | | | | Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
* [mips] not instruction aliasSimon Dardis2016-11-161-0/+2
| | | | | | | | | | | This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-142-7/+20
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-132-0/+10
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-0/+4
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-4/+0
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-271-0/+4
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-162-20/+7
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-162-7/+20
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga2016-08-221-0/+48
| | | | | | | | disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
* [mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis2016-08-171-0/+4
| | | | | | | | Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-272-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis2016-07-261-0/+11
| | | | | | | | | | | Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-111-0/+36
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga2016-06-271-0/+16
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850
* [mips] Remove tests which should have been deleted.Simon Dardis2016-05-311-19/+0
| | | | | | | The two xfail tests for mis32r6 & mips64r6 were supposed to be removed in r271301. llvm-svn: 271306
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-312-10/+24
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-271-0/+22
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan2016-05-181-0/+16
| | | | | | | | CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-121-2/+1
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-111-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
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