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* [MIPS][ELF] Use PC-relative relocations in .eh_frame when possibleAlex Richardson2020-01-131-35/+75
| | | | | | | | | | | | | | | | | | | | When compiling position-independent executables, we now use DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the large code model case. When using the large code model, we fall back to the previous behaviour of generating absolute relocations. With this change clang-generated .o files can be linked by LLD without having to pass -Wl,-z,notext (which creates text relocations). This is simpler than the approach used by ld.bfd, which rewrites the .eh_frame section to convert absolute relocations into relative references. I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations for MIPS ouput at some point. However, I also checked that recent ld.bfd can process the clang-generated .o files so this no longer seems true. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72228
* [mips] Fix sc, scs, ll, lld instructions expandingSimon Atanasyan2019-11-274-42/+1182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of bugs with the sc, scs, ll, lld instructions expanding: 1. On R6 these instruction pack immediate offset into a 9-bit field. Now if an immediate exceeds 9-bits assembler does not perform expansion and just rejects such instruction. 2. On 64-bit non-PIC code if an operand is a symbol assembler generates incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16 relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones. To solve these problems this patch: - Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands which require expansion. Probably later all `mem_simm9` operands will be able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`. - Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the `mem_simm9_exp`. That allows to know operand size in the `processInstruction` method and decide whether we need to expand instruction. - Adds `expandMem9Inst` method to expand instructions with 9-bit memory immediate operand. This method just load immediate into a "base" register used by origibal instruction: sc $2, 256($sp) => addiu $1, $sp, 256 sc $2, 0($1) - Fix `expandMem16Inst` to support a correct set of relocations for symbol loading in case of 64-bit non-PIC code. ll $12, symbol => lui $12, 0 R_MIPS_HIGHEST symbol daddiu $12, $12, 0 R_MIPS_HIGHER symbol dsll $12, $12, 16 daddiu $12, $12, 0 R_MIPS_HI16 symbol dsll $12, $12, 16 ll $12, 0($12) R_MIPS_LO16 symbol - Fix `expandMem16Inst` to unify handling of 3 and 4 operands instructions. - Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method. Task for next patches - implement expanding for other instructions use `mem_simm9` operand and other `mem_simm##` operands. Differential Revision: https://reviews.llvm.org/D70648
* [mips] Split test into MIPS and microMIPS parts. NFCSimon Atanasyan2019-11-252-26/+34
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* [mips] Rename test case. NFCSimon Atanasyan2019-11-211-0/+0
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* [mips] Remove addresses from the test case. NFCSimon Atanasyan2019-11-211-40/+40
| | | | It reduces "diff" after addition more tests in the future.
* [llvm-objdump] Print relocation addends in hexadecimalDavid Bozier2019-11-191-4/+4
| | | | | | | | | | | | | | Summary: Matches GNU objdump. Makes debugging easier for me as I'm working out addresses from symbol+addend, so it would be good to be calculating in a single format. Reviewers: MaskRay, grimar, jhenderson, bd1976llvm Reviewed By: jhenderson Subscribers: sdardis, jrtc27, atanasyan, rupprecht, seiya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69997
* [mips] Enable `la` pseudo instruction on 64-bit arch.Simon Atanasyan2019-11-152-8/+485
| | | | | | | This patch makes LLVM compatible with GAS. It accepts `la` pseudo instruction on arch with 64-bit pointers and just shows a warning. Differential Revision: https://reviews.llvm.org/D70202
* [mips] Do not emit R_MIPS_JALR for sym+offset in case of O32 ABISimon Atanasyan2019-11-151-61/+61
| | | | | | | | | | O32 ABI uses relocations in REL format. Relocation's addend is written in place. R_MIPS_JALR relocation points to the `jalr` instruction which does not have a place to store the relocation addend. So it's impossible to save non-zero "offset". This patch blocks emission of `R_MIPS_JALR` relocations in such cases. Differential Revision: https://reviews.llvm.org/D70201
* [mips] Add test to check ELF output for JAL XGOT expansion. NFCSimon Atanasyan2019-11-131-0/+216
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* [mips] Add tests to check `jal sym+offset`. NFCSimon Atanasyan2019-11-131-59/+401
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* [mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` sectionSimon Atanasyan2019-11-071-0/+6
| | | | Differential Revision: https://reviews.llvm.org/D69851
* [mips] Support `octeon+` CPU in the `.set arch=` directiveSimon Atanasyan2019-11-071-0/+4
| | | | Differential Revision: https://reviews.llvm.org/D69850
* [mips] Implement Octeon+ `saa` and `saad` instructionsSimon Atanasyan2019-11-076-0/+214
| | | | | | | | | | | | | | | `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
* [mips] Move test case for Octeon instructions to cnmips sub-folder. NFCSimon Atanasyan2019-11-041-0/+0
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* [mips] Use `expandLoadAddress` for JAL expansionSimon Atanasyan2019-10-231-0/+93
| | | | | - Reduce code duplication - Get partial support of JAL expansion for XGOT.
* [mips] Implement `la` macro expansion for N32 ABISimon Atanasyan2019-10-231-10/+83
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* [mips] Add tests to check `la / dla` expansion in XGOT cases. NFCSimon Atanasyan2019-10-232-0/+196
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* [mips] Reformat `la / dla` expansion test cases. NFCSimon Atanasyan2019-10-232-96/+149
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* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-233-19/+41
| | | | | | | | | | MipsMCAsmInfo was using '$' prefix for Mips32 and '.L' for Mips64 regardless of -target-abi option. By passing MCTargetOptions to MCAsmInfo we can find out Mips ABI and pick appropriate prefix. Tags: #llvm, #clang, #lldb Differential Revision: https://reviews.llvm.org/D66795
* [mips] Fix `loadImmediate` calls when load non-address values.Simon Atanasyan2019-10-121-2/+2
| | | | llvm-svn: 374640
* [mips] Store 64-bit `li.d' operand as a single 8-byte valueSimon Atanasyan2019-10-111-65/+65
| | | | | | | | | | | | | | | Now assembler generates two consecutive `.4byte` directives to store 64-bit `li.d' operand. The first directive stores high 4-byte of the value. The second directive stores low 4-byte of the value. But on 64-bit system we load this value at once and get wrong result if the system is little-endian. This patch fixes the bug. It stores the `li.d' operand as a single 8-byte value. Differential Revision: https://reviews.llvm.org/D68778 llvm-svn: 374598
* [mips] Use less instruction to load zero into FPR by li.s / li.d pseudosSimon Atanasyan2019-10-112-16/+8
| | | | | | | | | | If `li.s` or `li.d` loads zero into a FPR, it's not necessary to load zero into `at` GPR register and then move its value into a floating point register. We can use as a source register the `zero / $0` one. Differential Revision: https://reviews.llvm.org/D68777 llvm-svn: 374597
* [mips] Follow-up to r374544. Fix test case.Simon Atanasyan2019-10-111-2/+2
| | | | llvm-svn: 374548
* [mips] Fix loading "double" immediate into a GPR and FPRSimon Atanasyan2019-10-111-12/+22
| | | | | | | | | | | | | | | If a "double" (64-bit) value has zero low 32-bits, it's possible to load such value into a GP/FP registers as an instruction immediate. But now assembler loads only high 32-bits of the value. For example, if a target register is GPR the `li.d $4, 1.0` instruction converts into the `lui $4, 16368` one. As a result, we get `0x3FF00000` in the register. While a correct representation of the `1.0` value is `0x3FF0000000000000`. The patch fixes that. Differential Revision: https://reviews.llvm.org/D68776 llvm-svn: 374544
* [Mips] Fix evaluating J-format branch targetsSimon Atanasyan2019-10-072-0/+34
| | | | | | | | | | | | J/JAL/JALX/JALS are absolute branches, but stay within the current 256 MB-aligned region, so we must include the high bits of the instruction address when calculating the branch target. Patch by James Clarke. Differential Revision: https://reviews.llvm.org/D68548 llvm-svn: 373906
* [mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructionsSimon Atanasyan2019-10-033-0/+30
| | | | llvm-svn: 373591
* [mips] Use llvm-readobj `-A` flag in test cases. NFCSimon Atanasyan2019-10-0314-17/+17
| | | | llvm-svn: 373589
* [mips] Expand 'lw/sw' instructions for 32-bit GOTSimon Atanasyan2019-09-182-2/+134
| | | | | | | | | | In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
* [mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFCSimon Atanasyan2019-09-182-73/+74
| | | | | | That simplify adding XGOT tests later. llvm-svn: 372219
* [mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instructionSimon Atanasyan2019-08-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | When a "base" in the `lw/sw $reg1, symbol($reg2)` instruction is a register and generated code is position independent, backend does not add the "base" value to the symbol address. ``` lw $reg1, %got(symbol)($gp) lw/sw $reg1, 0($reg1) ``` This patch fixes the bug and adds the missed `addu` instruction by passing `BaseReg` into the `loadAndAddSymbolAddress` routine and handles the case when the `BaseReg` is the zero register to escape redundant `move reg, reg` instruction: ``` lw $reg1, %got(symbol)($gp) addu $reg1, $reg1, $reg2 lw/sw $reg1, 0($reg1) ``` Differential Revision: https://reviews.llvm.org/D66894 llvm-svn: 370353
* [mips] Reduce number of instructions used for loading a global symbol's valueSimon Atanasyan2019-08-232-34/+28
| | | | | | | | | | | | | | | | | | | | | | Now `lw/sw $reg, sym+offset` pseudo instructions for global symbol `sym` are lowering into the following three instructions. ``` lw $reg, %got(symbol)($gp) addiu $reg, $reg, offset lw/sw $reg, 0($reg) ``` It's possible to reduce the number of instructions by taking the offset in account in the final `lw/sw` command. This patch implements that optimization. ``` lw $reg, %got(symbol)($gp) lw/sw $reg, offset($reg) ``` Differential Revision: https://reviews.llvm.org/D66553 llvm-svn: 369756
* [mips] Do not include offset into `%got` expression for global symbolsSimon Atanasyan2019-08-232-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | Now pseudo instruction `la $6, symbol+8($6)` is expanding into the following chain of commands: ``` lw $1, %got(symbol+8)($gp) addiu $1, $1, 8 addu $6, $1, $6 ``` This is incorrect. When a linker handles the `R_MIPS_GOT16` relocation, it does not expect to get any addend and breaks on assertion. Otherwise it has to create new GOT entry for each unique "sym + offset" pair. Offset for a global symbol should be added to result of loading GOT entry by a separate `add` command. The patch fixes the problem by stripping off an offset from the expression passed to the `%got`. That's interesting that even current code inserts a separate `add` command. Differential Revision: https://reviews.llvm.org/D66552 llvm-svn: 369755
* [Mips] Instruction `sc` now accepts symbol as an argumentSimon Atanasyan2019-08-071-0/+74
| | | | | | | | | | | | | Function MipsAsmParser::expandMemInst() did not properly handle instruction `sc` with a symbol as an argument because first argument would be counted twice. We add additional checks and handle this case separately. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D64252 llvm-svn: 368160
* [mips] Fix lowering load/store instruction in PIC caseSimon Atanasyan2019-08-012-0/+112
| | | | | | | | | | | | | | | | | | | | | If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
* [mips] Add (dis)assembler tests for beqzl and bnezl instructions. NFCSimon Atanasyan2019-07-271-0/+2
| | | | llvm-svn: 367168
* Revert "Reland [ELF] Loose a condition for relocation with a symbol"Vlad Tsyrklevich2019-07-222-4/+10
| | | | | | | This reverts commit r366686 as it appears to be causing buildbot failures on sanitizer-x86_64-linux-android and sanitizer-x86_64-linux. llvm-svn: 366708
* Reland [ELF] Loose a condition for relocation with a symbolNikola Prica2019-07-222-10/+4
| | | | | | | | | | | | | | | | | | | This patch was not the reason of the buildbot failure. Deleted code was introduced as a work around for a bug in the gold linker (http://sourceware.org/PR16794). Test case that was given as a reason for this part of code, the one on previous link, now works for the gold. This condition is too strict and when a code is compiled with debug info it forces generation of numerous relocations with symbol for architectures that do not have relocation addend. Reviewers: arsenm, espindola Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D64327 llvm-svn: 366686
* [mips] Implement .cplocal directiveSimon Atanasyan2019-07-172-0/+65
| | | | | | | | | | | | | | This directive forces to use the alternate register for context pointer. For example, this code: .cplocal $4 jal foo expands to: ld $25, %call16(foo)($4) jalr $25 Differential Revision: https://reviews.llvm.org/D64743 llvm-svn: 366300
* [mips] Print BEQZL and BNEZL pseudo instructionsSimon Atanasyan2019-07-153-26/+26
| | | | | | One of the reasons - to be compatible with GNU tools. llvm-svn: 366133
* Revert "[ELF] Loose a condition for relocation with a symbol"Nikola Prica2019-07-102-4/+10
| | | | | | | | This reverts commit 8507eca1647118e73435b0ce1de8a1952a021d01. Reveting due to some suspicious failurse in santizer-x86_64-linux. llvm-svn: 365685
* [ELF] Loose a condition for relocation with a symbolNikola Prica2019-07-102-10/+4
| | | | | | | | | | | | | | | | | Deleted code was introduced as a work around for a bug in the gold linker (http://sourceware.org/PR16794). Test case that was given as a reason for this part of code, the one on previous link, now works for the gold. This condition is too strict and when a code is compiled with debug info it forces generation of numerous relocations with symbol for architectures that do not have relocation addend. Reviewers: arsenm, espindola Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D64327 llvm-svn: 365618
* [mips] Implement sge/sgeu pseudo instructionsSimon Atanasyan2019-07-092-0/+72
| | | | | | | | | | The `sge/sgeu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than or equal `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64314 llvm-svn: 365476
* [mips] Implement sgt/sgtu pseudo instructions with immediate operandSimon Atanasyan2019-07-092-0/+49
| | | | | | | | | The `sgt/sgtu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64313 llvm-svn: 365475
* [mips] Mark the `lwupc` instruction as MIPS64 R6 onlySimon Atanasyan2019-06-193-6/+1
| | | | | | | | | | The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf llvm-svn: 363886
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
| | | | llvm-svn: 363538
* [Mips] Add s.d instruction alias for Mips1Simon Atanasyan2019-06-121-0/+13
| | | | | | | | | | | Add support for s.d instruction for Mips1 which expands into two swc1 instructions. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D63199 llvm-svn: 363184
* [mips] LLVM and GAS now use same instructions for CFA Definition. NFCISimon Atanasyan2019-05-153-9/+7
| | | | | | | | | | | | | LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set the register and offset for current CFA rule. We change it to `DW_CFA_def_cfa_register` which is the same one used by GAS that only changes the register but keeping the old offset. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D61899 llvm-svn: 360765
* [llvm-readobj] Change -t to --symbols in tests. NFCFangrui Song2019-05-015-5/+5
| | | | | | | | | | -t is --symbols in llvm-readobj but --section-details (unimplemented) in readelf. The confusing option should not be used since we aim for improving compatibility. Keep just one llvm-readobj -t use case in test/tools/llvm-readobj/symbols.test llvm-svn: 359661
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-0147-62/+62
| | | | | | | | | | We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
* [llvm-nm][llvm-readelf] Avoid single-dash -long-option in testsFangrui Song2019-04-271-3/+2
| | | | llvm-svn: 359383
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