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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-13 12:12:56 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-13 12:12:56 +0000 |
| commit | 515e8699f459e7519546bc4dc1907a71b5325d55 (patch) | |
| tree | 7b5bdcfd8615b0ed68e4afd4a928e669fe51f301 /llvm/test/MC/Mips/mips64r6 | |
| parent | a0c82e18d54da3c1f0aa60091a05e6b9e4a84b68 (diff) | |
| download | bcm5719-llvm-515e8699f459e7519546bc4dc1907a71b5325d55.tar.gz bcm5719-llvm-515e8699f459e7519546bc4dc1907a71b5325d55.zip | |
[mips] Add IAS support for dvp, evp
These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.
Reviewers: vkalintiris
Differential Review: https://reviews.llvm.org/D24291
llvm-svn: 284115
Diffstat (limited to 'llvm/test/MC/Mips/mips64r6')
| -rw-r--r-- | llvm/test/MC/Mips/mips64r6/invalid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips64r6/valid.s | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s index 1fdcca9f440..636b2ddbff9 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid.s +++ b/llvm/test/MC/Mips/mips64r6/invalid.s @@ -116,6 +116,12 @@ local_label: dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate + dvp $17, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dvp $17, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dvp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + evp $16, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + evp $16, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s index 7ad4dc3c3d2..15c8da150a0 100644 --- a/llvm/test/MC/Mips/mips64r6/valid.s +++ b/llvm/test/MC/Mips/mips64r6/valid.s @@ -130,9 +130,13 @@ a: dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dvp $4 # CHECK: dvp $4 # encoding: [0x41,0x64,0x00,0x24] + dvp # CHECK: dvp $zero # encoding: [0x41,0x60,0x00,0x24] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58] + evp $5 # CHECK: evp $5 # encoding: [0x41,0x65,0x00,0x04] + evp # CHECK: evp $zero # encoding: [0x41,0x60,0x00,0x04] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] |
