| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Introduce codegen patterns for RV64M-only instructions | Alex Bradbury | 2019-01-12 | 1 | -0/+38 |
| * | [RISCV] Expand function call to "call" pseudoinstruction | Shiva Chen | 2018-04-25 | 1 | -6/+2 |
| * | [RISCV] Codegen support for the standard RV32M instruction set extension | Alex Bradbury | 2018-01-18 | 1 | -1/+13 |
| * | [RISCV] Implement frame pointer elimination | Alex Bradbury | 2018-01-18 | 1 | -6/+0 |
| * | [RISCV] Enable emission of alias instructions by default | Alex Bradbury | 2017-12-15 | 1 | -4/+4 |
| * | [RISCV] Implement prolog and epilog insertion | Alex Bradbury | 2017-12-11 | 1 | -0/+10 |
| * | [RISCV] Support lowering FrameIndex | Alex Bradbury | 2017-12-11 | 1 | -4/+4 |
| * | [CodeGen] Unify MBB reference format in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-04 | 1 | -2/+2 |
| * | [RISCV] Support and tests for a variety of additional LLVM IR constructs | Alex Bradbury | 2017-11-21 | 1 | -0/+29 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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