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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 11:53:54 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 11:53:54 +0000 |
| commit | 660bcceccf85bfc2bbac4f28b87e94c1f3e82184 (patch) | |
| tree | f912cc41c2b4669b0c611f253189434ef857902d /llvm/test/CodeGen/RISCV/rem.ll | |
| parent | 775bb7437932ea6141c33ab63074640fb541997e (diff) | |
| download | bcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.tar.gz bcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.zip | |
[RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because
it's not possible to write a pattern that directly matches a frameindex.
Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.
Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can
make use of it in the RISC-V backend.
Differential Revision: https://reviews.llvm.org/D39848
llvm-svn: 320353
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rem.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rem.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll index c9e2a90521d..b30968a959c 100644 --- a/llvm/test/CodeGen/RISCV/rem.ll +++ b/llvm/test/CodeGen/RISCV/rem.ll @@ -5,11 +5,11 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: urem: ; RV32I: # %bb.0: -; RV32I-NEXT: sw ra, 12(s0) +; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: lui a2, %hi(__umodsi3) ; RV32I-NEXT: addi a2, a2, %lo(__umodsi3) ; RV32I-NEXT: jalr ra, a2, 0 -; RV32I-NEXT: lw ra, 12(s0) +; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: jalr zero, ra, 0 %1 = urem i32 %a, %b ret i32 %1 @@ -18,11 +18,11 @@ define i32 @urem(i32 %a, i32 %b) nounwind { define i32 @srem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: srem: ; RV32I: # %bb.0: -; RV32I-NEXT: sw ra, 12(s0) +; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: lui a2, %hi(__modsi3) ; RV32I-NEXT: addi a2, a2, %lo(__modsi3) ; RV32I-NEXT: jalr ra, a2, 0 -; RV32I-NEXT: lw ra, 12(s0) +; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: jalr zero, ra, 0 %1 = srem i32 %a, %b ret i32 %1 |
