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| author | Alex Bradbury <asb@lowrisc.org> | 2018-01-18 12:36:38 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-01-18 12:36:38 +0000 |
| commit | 921383828e0b5922965162d9c9470de1868d4a88 (patch) | |
| tree | a934f91dd86bf3acfc6e58ea2869ffb7986fda02 /llvm/test/CodeGen/RISCV/rem.ll | |
| parent | ba91a689a167970ad00d7ef5a920609e716abcdb (diff) | |
| download | bcm5719-llvm-921383828e0b5922965162d9c9470de1868d4a88.tar.gz bcm5719-llvm-921383828e0b5922965162d9c9470de1868d4a88.zip | |
[RISCV] Codegen support for the standard RV32M instruction set extension
llvm-svn: 322843
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rem.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rem.ll | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll index 21737c93a80..f9ef4c9c8e6 100644 --- a/llvm/test/CodeGen/RISCV/rem.ll +++ b/llvm/test/CodeGen/RISCV/rem.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32I +; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32IM %s define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: urem: @@ -13,6 +15,11 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret +; +; RV32IM-LABEL: urem: +; RV32IM: # %bb.0: +; RV32IM-NEXT: remu a0, a0, a1 +; RV32IM-NEXT: ret %1 = urem i32 %a, %b ret i32 %1 } @@ -28,6 +35,11 @@ define i32 @srem(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret +; +; RV32IM-LABEL: srem: +; RV32IM: # %bb.0: +; RV32IM-NEXT: rem a0, a0, a1 +; RV32IM-NEXT: ret %1 = srem i32 %a, %b ret i32 %1 } |
