summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/Mips/mips64shift.ll
Commit message (Collapse)AuthorAgeFilesLines
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-1/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-2/+2
| | | | llvm-svn: 273669
* [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructionsHrvoje Varga2016-06-161-14/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D16917 llvm-svn: 272876
* [mips] Optimize code generation for 64-bit variable shift instructions.Vasileios Kalintiris2015-04-211-2/+4
| | | | | | | | | | | | | | | | Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-191-4/+4
| | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
* Add definitions of Mips64 rotate instructions.Akira Hatanaka2011-09-301-1/+41
| | | | llvm-svn: 140870
* Check values of immediate operands.Akira Hatanaka2011-09-301-6/+6
| | | | llvm-svn: 140860
* Mips64 shift instructions.Akira Hatanaka2011-09-301-0/+64
llvm-svn: 140841
OpenPOWER on IntegriCloud