diff options
| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-04-21 10:49:03 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-04-21 10:49:03 +0000 |
| commit | 32177d6becc390a942ae07285484b088755f2747 (patch) | |
| tree | 62fd5a83fd9d62dd6bbf6a4ffda760901312f328 /llvm/test/CodeGen/Mips/mips64shift.ll | |
| parent | 50b88ddb87a587e586ca59e96ac4f06402136ca6 (diff) | |
| download | bcm5719-llvm-32177d6becc390a942ae07285484b088755f2747.tar.gz bcm5719-llvm-32177d6becc390a942ae07285484b088755f2747.zip | |
[mips] Optimize code generation for 64-bit variable shift instructions.
Summary:
The 64-bit version of the variable shift instructions uses the
shift_rotate_reg class which uses a GPR32Opnd to specify the variable
shift amount. With this patch we avoid the generation of a redundant
SLL instruction for the variable shift instructions in 64-bit targets.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7413
llvm-svn: 235376
Diffstat (limited to 'llvm/test/CodeGen/Mips/mips64shift.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/mips64shift.ll | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll index 45d1c953227..52c6f906639 100644 --- a/llvm/test/CodeGen/Mips/mips64shift.ll +++ b/llvm/test/CodeGen/Mips/mips64shift.ll @@ -65,7 +65,8 @@ entry: define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shr = lshr i64 %a0, %a1 %sub = sub i64 64, %a1 %shl = shl i64 %a0, %sub @@ -75,7 +76,8 @@ entry: define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shl = shl i64 %a0, %a1 %sub = sub i64 64, %a1 %shr = lshr i64 %a0, %sub |
