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authorAkira Hatanaka <ahatanaka@mips.com>2011-09-30 18:51:46 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-09-30 18:51:46 +0000
commit7ba8a8d656b4ef9413bd8b41274eeda06897dc37 (patch)
tree642e2977efdb54cb8069ccfb5e3845758cdaf8e8 /llvm/test/CodeGen/Mips/mips64shift.ll
parent24ff8346713d1ff9b5fbdf27dcc6e131846c68ed (diff)
downloadbcm5719-llvm-7ba8a8d656b4ef9413bd8b41274eeda06897dc37.tar.gz
bcm5719-llvm-7ba8a8d656b4ef9413bd8b41274eeda06897dc37.zip
Add definitions of Mips64 rotate instructions.
llvm-svn: 140870
Diffstat (limited to 'llvm/test/CodeGen/Mips/mips64shift.ll')
-rw-r--r--llvm/test/CodeGen/Mips/mips64shift.ll42
1 files changed, 41 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index 24decbb8f3f..cc5e5085614 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
@@ -62,3 +62,43 @@ entry:
%shr = lshr i64 %a0, 40
ret i64 %shr
}
+
+define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
+entry:
+; CHECK: drotrv
+ %shr = lshr i64 %a0, %a1
+ %sub = sub i64 64, %a1
+ %shl = shl i64 %a0, %sub
+ %or = or i64 %shl, %shr
+ ret i64 %or
+}
+
+define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
+entry:
+; CHECK: drotrv
+ %shl = shl i64 %a0, %a1
+ %sub = sub i64 64, %a1
+ %shr = lshr i64 %a0, %sub
+ %or = or i64 %shr, %shl
+ ret i64 %or
+}
+
+define i64 @f11(i64 %a0) nounwind readnone {
+entry:
+; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
+ %shr = lshr i64 %a0, 10
+ %shl = shl i64 %a0, 54
+ %or = or i64 %shr, %shl
+ ret i64 %or
+}
+
+define i64 @f12(i64 %a0) nounwind readnone {
+entry:
+; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22
+ %shl = shl i64 %a0, 10
+ %shr = lshr i64 %a0, 54
+ %or = or i64 %shl, %shr
+ ret i64 %or
+}
+
+
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