[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876

1 files changed, 15 insertions, 14 deletions

diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index 52c6f906639..e3d314946f6 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -1,64 +1,65 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsllv
+; ALL: dsllv
   %shl = shl i64 %a0, %a1
   ret i64 %shl
 }
 
 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrav
+; ALL: dsrav
   %shr = ashr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrlv
+; ALL: dsrlv
   %shr = lshr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shl = shl i64 %a0, 10
   ret i64 %shl
 }
 
 define i64 @f4(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = ashr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f5(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f6(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shl = shl i64 %a0, 40
   ret i64 %shl
 }
 
 define i64 @f7(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = ashr i64 %a0, 40
   ret i64 %shr
 }
 
 define i64 @f8(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = lshr i64 %a0, 40
   ret i64 %shr
 }
@@ -66,7 +67,7 @@ entry:
 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shr = lshr i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shl = shl i64 %a0, %sub
@@ -77,7 +78,7 @@ entry:
 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shl = shl i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shr = lshr i64 %a0, %sub
@@ -87,7 +88,7 @@ entry:
 
 define i64 @f11(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   %shl = shl i64 %a0, 54
   %or = or i64 %shr, %shl
@@ -96,7 +97,7 @@ entry:
 
 define i64 @f12(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; ALL:       drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
   %shl = shl i64 %a0, 10
   %shr = lshr i64 %a0, 54
   %or = or i64 %shl, %shr