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* Remove trailing whitespaceSimon Pilgrim2016-08-181-9/+9
* [WebAssembly] Handle debug information and virtual registers without crashing...Dominic Chen2016-08-173-3/+5
* Revert "[WebAssembly] Handle debug information and virtual registers without ...Duncan P. N. Exon Smith2016-08-173-5/+3
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1719-80/+119
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+1
* [WebAssembly] Handle debug information and virtual registers without crashingDominic Chen2016-08-173-3/+5
* AMDGPU: Remove dead optionMatt Arsenault2016-08-171-6/+0
* [mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis2016-08-171-0/+19
* [LoopStrenghtReduce] Refactoring and addition of a new target cost function.Jonas Paulsson2016-08-172-0/+24
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1735-95/+116
* [ppc64] Don't apply sibling call optimization if callee has any byval argChuang-Yu Cheng2016-08-171-1/+8
* [PM] Port the always inliner to the new pass manager in a much moreChandler Carruth2016-08-171-1/+2
* Some places that could using TargetParser in LLVM. NFC.Zijiao Ma2016-08-172-3/+8
* ARM: Avoid dereferencing end() in ARMFrameLowering::emitPrologueDuncan P. N. Exon Smith2016-08-171-1/+2
* Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranchDuncan P. N. Exon Smith2016-08-171-7/+5
* AMDGPU: Avoid looking for the DebugLoc in end()Duncan P. N. Exon Smith2016-08-171-14/+12
* [AMDGPU] Remove duplicate initialization of SIDebuggerInsertNops passKonstantin Zhuravlyov2016-08-161-1/+0
* [x86] Allow merging multiple instances of an immediate within a basic block f...Sanjay Patel2016-08-162-6/+9
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-14/+9
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-7/+11
* AMDGPU: Remove excessive padding from ImmOp and RegOp.Matt Arsenault2016-08-161-4/+4
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-1610-74/+67
* [mips] Enforce compact branch restrictionsSimon Dardis2016-08-161-13/+12
* [Hexagon] Clean up some miscellaneous V60 intrinsics a bitKrzysztof Parzyszek2016-08-166-69/+58
* [Hexagon] Standardize vector predicate load/store pseudo instructionsKrzysztof Parzyszek2016-08-163-67/+32
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+37
* [AArch64][GlobalISel] Factor out unsupported binop check. NFC.Ahmed Bougacha2016-08-161-40/+50
* [AArch64][GlobalISel] Select (variable) shifts.Ahmed Bougacha2016-08-162-0/+19
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-162-0/+20
* [x86] Refactor a PowerPC specific ctlz/srl transformation (NFC).Pierre Gousseau2016-08-162-13/+7
* [X86][SSE] Add support for combining v2f64 target shuffles to VZEXT_MOVL byte...Simon Pilgrim2016-08-161-3/+3
* Correct the upper bound for a CBZ/CBNZ branch target.Prakhar Bahuguna2016-08-161-2/+4
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-162-0/+11
* [X86][SSE] Add support for combining target shuffles to PALIGNR byte rotationsSimon Pilgrim2016-08-161-22/+55
* [AVR] Fix compile errorsJob Noorman2016-08-162-5/+5
* [X86] Add xgetbv/xsetbv intrinsics to non-windows platformsGuy Blank2016-08-163-3/+61
* [AMDGPU] Give enum an explicit 64-bit type to fix MSVC 2013 failuresReid Kleckner2016-08-151-1/+1
* AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely2016-08-154-183/+110
* Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions."Matthias Braun2016-08-152-11/+0
* AMDGPU: Update AMDGPURuntimeMetadata.h for enums of address space qualifiersYaxun Liu2016-08-151-0/+7
* AMDGPU: Don't fold subregister extracts into tied operandsMatt Arsenault2016-08-151-3/+15
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
* MachineLoop: add methods findLoopControlBlock and findLoopPreheaderSjoerd Meijer2016-08-151-62/+11
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-152-0/+11
* [X86] PADDUSB/W instructions should be commutable.Craig Topper2016-08-151-2/+2
* [X86] Mark some of the X86 SDNodes as commutative.Craig Topper2016-08-151-8/+10
* [X86] X86ISD::FANDN is not commutative or associative.Craig Topper2016-08-151-2/+1
* [AVX-512] Mark VPMADDWD as commutable to match SSE/AVX version.Craig Topper2016-08-141-7/+8
* [AVX-512] Add masked commutable floating point max/min instructions to foldin...Craig Topper2016-08-141-0/+24
* [AVX-512] Add masked logical operations to memory folding tables.Craig Topper2016-08-141-2/+98
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