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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-08-18 11:22:22 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-08-18 11:22:22 +0000 |
| commit | 916485c765defd52c54e9e050c7845196d65aff8 (patch) | |
| tree | 2398427dab5adbe22d0205e51e0f141b522945c9 /llvm/lib/Target | |
| parent | 9405ae704beaf2e47121e41f3042e819d8db507a (diff) | |
| download | bcm5719-llvm-916485c765defd52c54e9e050c7845196d65aff8.tar.gz bcm5719-llvm-916485c765defd52c54e9e050c7845196d65aff8.zip | |
Remove trailing whitespace
llvm-svn: 279054
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index be4834c32df..b387d0cd7fd 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -285,7 +285,7 @@ multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _, multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _, dag Outs, dag NonTiedIns, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, bit IsCommutable = 0, + dag RHS, bit IsCommutable = 0, bit IsKCommutable = 0> : AVX512_maskable_common<O, F, _, Outs, !con((ins _.RC:$src1), NonTiedIns), @@ -1292,7 +1292,7 @@ multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> { (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"), - [(set _.RC:$dst, (vselect _.KRCWM:$mask, + [(set _.RC:$dst, (vselect _.KRCWM:$mask, (_.VT _.RC:$src2), (_.VT _.RC:$src1)))]>, EVEX_4V, EVEX_K; let hasSideEffects = 0 in @@ -2562,14 +2562,14 @@ def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))), // Patterns for kmask shift multiclass mask_shift_lowering<RegisterClass RC, ValueType VT> { def : Pat<(VT (X86vshli RC:$src, (i8 imm:$imm))), - (VT (COPY_TO_REGCLASS + (VT (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS RC:$src, VK16), - (I8Imm $imm)), + (I8Imm $imm)), RC))>; def : Pat<(VT (X86vsrli RC:$src, (i8 imm:$imm))), - (VT (COPY_TO_REGCLASS + (VT (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS RC:$src, VK16), - (I8Imm $imm)), + (I8Imm $imm)), RC))>; } @@ -5461,14 +5461,14 @@ let Predicates = [HasAVX512] in { !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>, EVEX; - + def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", (!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>; def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}", (!cast<Instruction>(NAME # "rb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>; def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", - (!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst, - _SrcRC.ScalarMemOp:$src), 0>; + (!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst, + _SrcRC.ScalarMemOp:$src), 0>; let isCodeGenOnly = 1 in { def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), |
