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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-08-16 12:52:06 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-08-16 12:52:06 +0000 |
| commit | cc316f013a72e49ec97ad7f50164be88f611b941 (patch) | |
| tree | 48280f4656f8763bfe59087e6ec13e56177eced3 /llvm/lib/Target | |
| parent | 49307c02970ff0284a439108fb476d4da2c508d6 (diff) | |
| download | bcm5719-llvm-cc316f013a72e49ec97ad7f50164be88f611b941.tar.gz bcm5719-llvm-cc316f013a72e49ec97ad7f50164be88f611b941.zip | |
[X86][SSE] Add support for combining v2f64 target shuffles to VZEXT_MOVL byte rotations
The combine was only matching v2i64 as it assumed lowering to MOVQ - but we have v2f64 patterns that match in a similar fashion
llvm-svn: 278794
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 04b068f834c..50146804ae8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24884,11 +24884,11 @@ static bool matchUnaryVectorShuffle(MVT MaskVT, ArrayRef<int> Mask, bool FloatDomain = MaskVT.isFloatingPoint() || (!Subtarget.hasAVX2() && MaskVT.is256BitVector()); - // Match a 128-bit integer vector against a VZEXT_MOVL (MOVQ) instruction. - if (!FloatDomain && MaskVT.is128BitVector() && + // Match a 128-bit vector against a VZEXT_MOVL instruction. + if (MaskVT.is128BitVector() && Subtarget.hasSSE2() && isTargetShuffleEquivalent(Mask, {0, SM_SentinelZero})) { Shuffle = X86ISD::VZEXT_MOVL; - ShuffleVT = MVT::v2i64; + ShuffleVT = MaskVT; return true; } |
