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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-16 14:02:47 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-16 14:02:47 +0000 |
| commit | 2ac5bf94bcaf5617a2f7efcefa2f16755faea8e2 (patch) | |
| tree | 273e8fa9b10e604f843e240f702ea039625633a3 /llvm/lib/Target | |
| parent | 7e508a8fcd3bfb29b5612cce787e55d4e71d373c (diff) | |
| download | bcm5719-llvm-2ac5bf94bcaf5617a2f7efcefa2f16755faea8e2.tar.gz bcm5719-llvm-2ac5bf94bcaf5617a2f7efcefa2f16755faea8e2.zip | |
[AArch64][GlobalISel] Select (variable) shifts.
For now, no support for immediates.
llvm-svn: 278804
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 15 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp | 4 |
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index d12c7e12755..dad18fd8e88 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -60,6 +60,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ADDWrr; case TargetOpcode::G_SUB: return AArch64::SUBWrr; + case TargetOpcode::G_SHL: + return AArch64::LSLVWr; + case TargetOpcode::G_LSHR: + return AArch64::LSRVWr; + case TargetOpcode::G_ASHR: + return AArch64::ASRVWr; default: return GenericOpc; } @@ -75,6 +81,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ADDXrr; case TargetOpcode::G_SUB: return AArch64::SUBXrr; + case TargetOpcode::G_SHL: + return AArch64::LSLVXr; + case TargetOpcode::G_LSHR: + return AArch64::LSRVXr; + case TargetOpcode::G_ASHR: + return AArch64::ASRVXr; default: return GenericOpc; } @@ -190,6 +202,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_OR: case TargetOpcode::G_XOR: case TargetOpcode::G_AND: + case TargetOpcode::G_SHL: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_ASHR: case TargetOpcode::G_ADD: case TargetOpcode::G_SUB: { DEBUG(dbgs() << "AArch64: Selecting: binop\n"); diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp index fc73215967c..989aeb2f951 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp @@ -42,6 +42,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() { setAction(BinOp, Ty, WidenScalar); } + for (auto BinOp : {G_SHL, G_LSHR, G_ASHR}) + for (auto Ty : {s32, s64}) + setAction(BinOp, Ty, Legal); + for (auto MemOp : {G_LOAD, G_STORE}) for (auto Ty : {s32, s64}) setAction(MemOp, Ty, Legal); |

