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* [ARM] Split Arm jump table branch into i12 and rs suffixed versionsMomchil Velikov2017-11-155-210/+33
* [X86] Redefine the 128-bit version of VPGATHERQD and VGATHERQPS to use a VK2 ...Craig Topper2017-11-153-14/+24
* [PowerPC] fix up in redundant compare eliminationHiroshi Inoue2017-11-151-2/+6
* AMDGPU: Add separate definitions for DS insts without m0 useMatt Arsenault2017-11-151-154/+207
* AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault2017-11-156-2/+60
* AMDGPU: Handle or in multi-use shl ptr combineMatt Arsenault2017-11-141-2/+2
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-147-1/+375
* Fix unused variable warning.Richard Smith2017-11-141-1/+0
* AMDGPU: Error on stack size overflowMatt Arsenault2017-11-142-6/+12
* [SystemZ] Do not crash when selecting an OR of two constantsUlrich Weigand2017-11-141-2/+4
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-141-11/+9
* [ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting...Martin Storsjo2017-11-142-2/+4
* [SystemZ] Fix invalid codegen using RISBMux on out-of-range bitsUlrich Weigand2017-11-141-1/+9
* Mark intrinsics operating on the whole warp as IntrInaccessibleMemOnlyArtem Belevich2017-11-142-10/+21
* [X86] Fix typo in comment. NFCCraig Topper2017-11-141-2/+2
* ARM: correctly update CFG when splitting BB to fix branch.Tim Northover2017-11-141-0/+6
* [ARM GlobalISel] Remove C++ code for G_CONSTANTDiana Picus2017-11-141-22/+0
* [ARM] Fix incorrect conversion of a tail call to an ordinary callMomchil Velikov2017-11-142-36/+74
* AMDGPU: Fix producing saveexec when the copy is spilledMatt Arsenault2017-11-141-2/+16
* Update some code.google.com linksHans Wennborg2017-11-131-1/+1
* AMDGPU: Fix not converting d16 load/stores to offsetMatt Arsenault2017-11-131-1/+22
* AMDGPU: Implement computeKnownBitsForTargetNode for mbcntMatt Arsenault2017-11-132-0/+18
* [arm] Fix Unnecessary reloads from GOT.Evgeniy Stepanov2017-11-139-40/+41
* [X86] Allow X86ISD::Wrapper to be folded into the base of gather/scatter addressCraig Topper2017-11-131-20/+35
* AMDGPU: Drop duplicate setOperationActionJan Vesely2017-11-131-2/+0
* [X86] test/testn intrinsics lowering to IR. llvm part.Uriel Korach2017-11-131-24/+0
* [ARM] Place jump table as the first operand in additionsMomchil Velikov2017-11-133-10/+10
* Test commitSander de Smalen2017-11-131-1/+1
* [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IRJina Nahias2017-11-131-16/+0
* [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.Gadi Haber2017-11-131-102/+102
* [X86] Limit NOPs to 7 bytes when 'slm' is spelled 'silvermont'.Craig Topper2017-11-131-1/+1
* [X86] Use sse_load_f32/f64 to improve load folding of scalar vfscalefss/sd, v...Craig Topper2017-11-131-5/+4
* [X86] Use sse_load_f32/f64 to improve load folding for scalar VFPCLASS intrin...Craig Topper2017-11-131-4/+4
* AMDGPU: Preserve nuw in shl add ptr combineMatt Arsenault2017-11-131-1/+6
* [X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_load_f32/sse_load_f...Craig Topper2017-11-132-10/+13
* AMDGPU: Fix multi-use shl/add combineMatt Arsenault2017-11-132-31/+15
* [X86] Attempt to fix signed and unsigned comparison warning.Craig Topper2017-11-131-2/+2
* [X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.Craig Topper2017-11-131-3/+2
* [X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round i...Craig Topper2017-11-134-29/+55
* [X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes into versions with an...Craig Topper2017-11-135-99/+157
* AMDGPU: Select d16 loads into low component of registerMatt Arsenault2017-11-136-5/+147
* [X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.Craig Topper2017-11-125-6/+8
* [X86] Remove some no longer needed intrinsic lowering code.Craig Topper2017-11-122-18/+1
* [llvm] Remove redundant return [NFC]Mandeep Singh Grang2017-11-122-2/+0
* [X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint whe...Craig Topper2017-11-112-1/+47
* [X86] Attempt to match multiple binary reduction ops at once. NFCISimon Pilgrim2017-11-111-61/+67
* [X86] Add scalar register class versions of VRNDSCALE instructions and rename...Craig Topper2017-11-112-36/+56
* [X86] Inline some SDNode operand multiclass operands that don't vary. NFCCraig Topper2017-11-111-33/+28
* [X86] Set the execution domain for VFPCLASS to SSEPackedSingle/Double.Craig Topper2017-11-111-1/+3
* [X86] Set the execution domain for vptest instruction to the integer domain.Craig Topper2017-11-111-0/+3
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