| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [X86] Add register use/def for wrmsr and rdmsr. | Craig Topper | 2015-02-07 | 1 | -0/+2 |
| * | [X86] Add GETSEC instruction. | Craig Topper | 2015-02-07 | 1 | -0/+6 |
| * | [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions | Craig Topper | 2015-02-05 | 1 | -2/+15 |
| * | [X86] Remove two feature flags that covered sets of instructions that have no... | Craig Topper | 2015-02-05 | 1 | -1/+1 |
| * | [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T ... | Craig Topper | 2015-02-03 | 1 | -3/+3 |
| * | Use a different encoding for debugtrap on PS4. | Alex Rosenberg | 2015-01-26 | 1 | -3/+4 |
| * | [X86] Clean up whitespace as well as minor coding style | Michael Liao | 2014-12-04 | 1 | -14/+14 |
| * | X86: cpuid and xgetbv write to 32-bit registers, not 64-bit | Reid Kleckner | 2014-09-04 | 1 | -7/+3 |
| * | [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes | Robert Khasanov | 2014-08-21 | 1 | -1/+1 |
| * | [X86] Add support for builtin to read performance monitoring counters. | Andrea Di Biagio | 2014-06-30 | 1 | -1/+4 |
| * | [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics. | Andrea Di Biagio | 2014-04-24 | 1 | -1/+1 |
| * | [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS | Craig Topper | 2014-02-27 | 1 | -6/+0 |
| * | [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency. | Craig Topper | 2014-02-26 | 1 | -2/+2 |
| * | Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0x... | Craig Topper | 2014-02-19 | 1 | -9/+9 |
| * | Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ... | Craig Topper | 2014-02-18 | 1 | -6/+10 |
| * | Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ... | Craig Topper | 2014-02-02 | 1 | -77/+81 |
| * | Simplify some x86 format classes and remove some ambiguities in their applica... | Craig Topper | 2014-02-01 | 1 | -8/+8 |
| * | x86: add implicit defs for cpuid | Reid Kleckner | 2014-01-28 | 1 | -2/+7 |
| * | [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 | 1 | -3/+6 |
| * | Switch a few instructions to use RI instead I so they don't require REX_W to ... | Craig Topper | 2014-01-17 | 1 | -6/+6 |
| * | Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ... | Craig Topper | 2014-01-14 | 1 | -2/+2 |
| * | [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases | David Woodhouse | 2014-01-08 | 1 | -8/+16 |
| * | [x86] Add OpSize16 to instructions that need it | David Woodhouse | 2014-01-08 | 1 | -47/+58 |
| * | Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. R... | Craig Topper | 2014-01-04 | 1 | -10/+18 |
| * | Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack fro... | Craig Topper | 2014-01-02 | 1 | -4/+4 |
| * | [x86] Rename In32BitMode predicate to Not64BitMode | Eric Christopher | 2013-12-20 | 1 | -23/+23 |
| * | Changed register names (and pointer keywords) to be lower case when using Int... | Craig Topper | 2013-07-31 | 1 | -38/+38 |
| * | Add CLAC/STAC instruction encoding/decoding support | Michael Liao | 2013-04-11 | 1 | -0/+7 |
| * | fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases | Kay Tiong Khoo | 2013-04-10 | 1 | -3/+3 |
| * | fixed to disassemble with tab after mnemonic rather than space | Kay Tiong Khoo | 2013-04-10 | 1 | -2/+2 |
| * | Add a catch-all WriteSystem SchedWrite type. | Jakob Stoklund Olesen | 2013-03-20 | 1 | -1/+23 |
| * | *fixed disassembly of some i386 system insts with intel syntax | Kay Tiong Khoo | 2013-02-11 | 1 | -4/+4 |
| * | Rename @llvm.debugger to @llvm.debugtrap. | Dan Gohman | 2012-05-14 | 1 | -1/+1 |
| * | Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), | Dan Gohman | 2012-05-11 | 1 | -0/+3 |
| * | Adds Intel Atom scheduling latencies to X86InstrSystem.td. | Preston Gurd | 2012-05-04 | 1 | -138/+152 |
| * | Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax. | Bill Wendling | 2012-03-10 | 1 | -5/+5 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -3/+3 |
| * | Fix asm string wrt variants. | Devang Patel | 2012-01-09 | 1 | -6/+6 |
| * | Add intrinsics and feature flag for read/write FS/GS base instructions. Also ... | Craig Topper | 2011-10-30 | 1 | -13/+21 |
| * | Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and | Kevin Enderby | 2011-10-27 | 1 | -3/+2 |
| * | Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMR... | Craig Topper | 2011-10-16 | 1 | -0/+9 |
| * | Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. | Craig Topper | 2011-10-07 | 1 | -0/+23 |
| * | Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. | Craig Topper | 2011-10-07 | 1 | -0/+15 |
| * | Fix register printing in disassembling of push/pop of segment registers and i... | Craig Topper | 2011-09-22 | 1 | -38/+38 |
| * | Recognize the xstorerng alias for VIA PadLock's xstore instruction. | Joerg Sonnenberger | 2011-06-30 | 1 | -0/+2 |
| * | fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, | Chris Lattner | 2011-04-09 | 1 | -0/+7 |
| * | Add support for the VIA PadLock instructions. | Joerg Sonnenberger | 2011-04-04 | 1 | -0/+20 |
| * | PR9377: Handle x86 str with register operand in a way consistent with gas. | Eli Friedman | 2011-03-04 | 1 | -4/+9 |
| * | Implement xgetbv and xsetbv. | Rafael Espindola | 2011-02-22 | 1 | -0/+5 |
| * | Added the x86 instruction ud2b (2nd official undefined instruction). | Kevin Enderby | 2010-10-27 | 1 | -1/+3 |
