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authorKevin Enderby <enderby@apple.com>2010-10-27 20:46:49 +0000
committerKevin Enderby <enderby@apple.com>2010-10-27 20:46:49 +0000
commit5e7cb5fc273f23ba0f5780a38564834cdf14db5a (patch)
tree1b795f085017f76e734d16ad62414a1ae3aa9481 /llvm/lib/Target/X86/X86InstrSystem.td
parentdd6907bd7757eaed3cf127399b78601bf2ca8d5d (diff)
downloadbcm5719-llvm-5e7cb5fc273f23ba0f5780a38564834cdf14db5a.tar.gz
bcm5719-llvm-5e7cb5fc273f23ba0f5780a38564834cdf14db5a.zip
Added the x86 instruction ud2b (2nd official undefined instruction).
llvm-svn: 117485
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSystem.td')
-rw-r--r--llvm/lib/Target/X86/X86InstrSystem.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 48b6d6ecf07..1a58ba0f96e 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -21,8 +21,10 @@ let Defs = [RAX, RCX, RDX] in
// CPU flow control instructions
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
+ def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
+}
def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
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