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| author | Michael Liao <michael.liao@intel.com> | 2013-04-11 04:52:28 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-04-11 04:52:28 +0000 |
| commit | 95d9440348a8437fb792052a2238d972bf884bda (patch) | |
| tree | 24fe120bb8bb01995a477832557bd1e1feff757d /llvm/lib/Target/X86/X86InstrSystem.td | |
| parent | f7bf87051acf39128aeb8ce7305a6d58067ac5ac (diff) | |
| download | bcm5719-llvm-95d9440348a8437fb792052a2238d972bf884bda.tar.gz bcm5719-llvm-95d9440348a8437fb792052a2238d972bf884bda.zip | |
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
llvm-svn: 179266
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSystem.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSystem.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index 869304d1b4c..bab3cdd0009 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -520,3 +520,10 @@ def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), "invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8, Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// SMAP Instruction +let Defs = [EFLAGS], Uses = [EFLAGS] in { + def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; + def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; +} |
