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path: root/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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* [WebAssembly] Narrowing and widening SIMD opsThomas Lively2019-09-131-0/+36
* [WebAssembly] Add SIMD QFMA/QFMSThomas Lively2019-08-311-0/+21
* [WebAssembly] Omit wrap on i64x2.{shl,shr*} ISel when possibleThomas Lively2019-06-261-2/+8
* [WebAssembly] Optimize ISel for SIMD Boolean reductionsThomas Lively2019-06-191-0/+22
* [WebAssembly] Lower SIMD nnan setcc nodesThomas Lively2019-03-191-10/+12
* [WebAssembly] Remove unused load/store patterns that use texternalsymSam Clegg2019-03-151-4/+0
* [WebAssembly] Use named operands to identify loads and storesThomas Lively2019-03-091-10/+10
* [WebAssembly] Tidy up `let` statements in .td files (NFC)Heejin Ahn2019-02-061-3/+2
* [WebAssembly] Fix indentation after adding IsCanonical property (NFC)Heejin Ahn2019-02-051-4/+4
* [WebAssembly] Make disassembler always emit most canonical name.Wouter van Oortmerssen2019-02-051-4/+6
* [WebAssembly] Fix a regression selecting negative build_vector lanesThomas Lively2019-01-311-1/+1
* [WebAssembly] Optimize BUILD_VECTOR lowering for sizeThomas Lively2019-01-301-112/+0
* [WebAssembly] Lower SCALAR_TO_VECTOR to splatsThomas Lively2019-01-291-0/+13
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [WebAssembly] Add unimplemented-simd128 subtarget featureThomas Lively2019-01-101-4/+4
* [WebAssembly] Standardize order of SIMD bitselect argumentsThomas Lively2019-01-091-1/+1
* [WebAssembly] Massive instruction renamingThomas Lively2019-01-081-11/+11
* [WebAssembly] Gate unimplemented SIMD ops on flagThomas Lively2018-12-201-4/+9
* [WebAssembly] Renumber SIMD bitwise instructionsThomas Lively2018-11-151-7/+7
* [WebAssembly][NFC] Reorder SIMD sectionThomas Lively2018-11-091-283/+270
* [WebAssembly] Renumber and LEB128-encode SIMD opcodesThomas Lively2018-11-091-138/+116
* [WebAssembly] Use target-independent saturating addThomas Lively2018-10-251-2/+2
* [WebAssembly] Retain shuffle types during custom loweringThomas Lively2018-10-241-3/+3
* [NFC] Rename minnan and maxnan to minimum and maximumThomas Lively2018-10-241-2/+2
* [WebAssembly] Implement vector sext_inreg and tests with comparisonsThomas Lively2018-10-201-4/+5
* [WebAssembly] Custom lower i64x2 constant shifts to avoid wrapThomas Lively2018-10-201-0/+13
* [WebAssembly] Handle undefined lane indices in SIMD patternsThomas Lively2018-10-191-0/+36
* [WebAssembly][NFC] Fix signed/unsigned comparison warningThomas Lively2018-10-131-1/+3
* [WebAssembly] SIMD min and maxThomas Lively2018-10-131-7/+7
* [WebAssembly][NFC] Unify ARGUMENT classesThomas Lively2018-10-131-15/+6
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS] (fixed)Thomas Lively2018-10-111-3/+2
* [WebAssembly] Revert rL344180, which was breaking expensive checksThomas Lively2018-10-111-0/+2
* [WebAssembly][NFC] Use intrinsic dag nodes directlyThomas Lively2018-10-111-25/+14
* [WebAssembly] Saturating float to int intrinsicsThomas Lively2018-10-111-0/+10
* [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS]Thomas Lively2018-10-101-2/+0
* [WebAssembly][NFC] Use vnot patfrag to simplify v128.notThomas Lively2018-10-101-14/+7
* [WebAssembly] Fix fneg loweringThomas Lively2018-10-101-28/+13
* [WebAssembly] Improve comments for SIMD instruction definitionsHeejin Ahn2018-10-101-2/+2
* [WebAssembly] Improve readability of SIMD instructions (NFC)Heejin Ahn2018-10-091-420/+586
* [WebAssembly] Saturating arithmetic intrinsicsThomas Lively2018-10-051-0/+15
* [WebAssembly] Bitselect intrinsic and instructionThomas Lively2018-10-031-0/+24
* [WebAssembly] any_true and all_true intrinsics and instructionsThomas Lively2018-10-031-2/+22
* [WebAssembly] Restore slashes in SIMD conversion namesThomas Lively2018-10-021-8/+8
* [WebAssembly] SIMD conversionsThomas Lively2018-09-261-0/+16
* [WebAssembly] SIMD sqrtThomas Lively2018-09-251-0/+9
* [WebAssembly] Renumber SIMD opsThomas Lively2018-09-201-35/+35
* [WebAssembly][NFC] Remove extra space in WebAssemblyInstrSIMD.tdThomas Lively2018-09-191-1/+1
* [WebAssembly] v4f32.abs and v2f64.absThomas Lively2018-09-181-0/+8
* [WebAssembly] SIMD shiftsThomas Lively2018-09-151-0/+26
* [WebAssembly] SIMD negThomas Lively2018-09-141-0/+30
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