diff options
| author | Thomas Lively <tlively@google.com> | 2019-03-19 00:55:34 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2019-03-19 00:55:34 +0000 |
| commit | 0200d62ec7a54b79313bc2c4ccbe51c2a8c5e940 (patch) | |
| tree | 4395820444a96c08761aaac1ac3800faab47869c /llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | |
| parent | dc087de14c2866c232be607be8ebbd8a876f70e7 (diff) | |
| download | bcm5719-llvm-0200d62ec7a54b79313bc2c4ccbe51c2a8c5e940.tar.gz bcm5719-llvm-0200d62ec7a54b79313bc2c4ccbe51c2a8c5e940.zip | |
[WebAssembly] Lower SIMD nnan setcc nodes
Summary:
Adds patterns to lower all the remaining setcc modes: lt, gt,
le, and ge. Fixes PR40912.
Reviewers: aheejin, sbc100, dschuff
Reviewed By: dschuff
Subscribers: jgravelle-google, hiraditya, sunfish, jdoerfert, llvm-commits, srj
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59519
llvm-svn: 356431
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 6f5e89efaf0..59b56cac5de 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -417,16 +417,18 @@ defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>; defm GE : SIMDConditionFP<"ge", SETOGE, 69>; // Lower float comparisons that don't care about NaN to standard WebAssembly -// float comparisons. These instructions are generated in the target-independent -// expansion of unordered comparisons and ordered ne. -def : Pat<(v4i32 (seteq (v4f32 V128:$lhs), (v4f32 V128:$rhs))), - (v4i32 (EQ_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; -def : Pat<(v4i32 (setne (v4f32 V128:$lhs), (v4f32 V128:$rhs))), - (v4i32 (NE_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; -def : Pat<(v2i64 (seteq (v2f64 V128:$lhs), (v2f64 V128:$rhs))), - (v2i64 (EQ_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; -def : Pat<(v2i64 (setne (v2f64 V128:$lhs), (v2f64 V128:$rhs))), - (v2i64 (NE_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; +// float comparisons. These instructions are generated with nnan and in the +// target-independent expansion of unordered comparisons and ordered ne. +foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32], + [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in +def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), + (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; + +foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64], + [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in +def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), + (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; + //===----------------------------------------------------------------------===// // Bitwise operations |
