diff options
| author | Thomas Lively <tlively@google.com> | 2018-12-20 02:10:22 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2018-12-20 02:10:22 +0000 |
| commit | 8dbf29af952b955b19b2ab6e87db6f406a8dcf4a (patch) | |
| tree | 19d76e0875c477bd2901e23c057e837677a30865 /llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | |
| parent | 6314b92331d0bf5518152540cfbcbd71548f5668 (diff) | |
| download | bcm5719-llvm-8dbf29af952b955b19b2ab6e87db6f406a8dcf4a.tar.gz bcm5719-llvm-8dbf29af952b955b19b2ab6e87db6f406a8dcf4a.zip | |
[WebAssembly] Gate unimplemented SIMD ops on flag
Summary:
Gates v128.const, f32x4.sqrt, f32x4.div, i8x16.extract_lane_u, and
i16x8.extract_lane_u on the --wasm-enable-unimplemented-simd flag,
since these ops are not implemented yet in V8.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D55904
llvm-svn: 349720
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 7ac2d15c295..08d6a5a6c83 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -94,7 +94,8 @@ def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>; // Constant: v128.const multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { - let isMoveImm = 1, isReMaterializable = 1 in + let isMoveImm = 1, isReMaterializable = 1, + Predicates = [HasSIMD128, HasUnimplementedSIMD] in defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, [(set V128:$dst, (vec_t pat))], "v128.const\t$dst, "#args, @@ -276,17 +277,19 @@ multiclass ExtractLaneExtended<string sign, bits<32> baseInst> { } defm "" : ExtractLaneExtended<"_s", 5>; +let Predicates = [HasSIMD128, HasUnimplementedSIMD] in defm "" : ExtractLaneExtended<"_u", 6>; defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>; defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>; defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>; defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>; -// Follow convention of making implicit expansions unsigned +// It would be more conventional to use unsigned extracts, but v8 +// doesn't implement them yet def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))), - (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>; + (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>; def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))), - (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>; + (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>; // Lower undef lane indices to zero def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)), @@ -725,6 +728,7 @@ defm ABS : SIMDUnaryFP<fabs, "abs", 149>; defm NEG : SIMDUnaryFP<fneg, "neg", 150>; // Square root: sqrt +let Predicates = [HasSIMD128, HasUnimplementedSIMD] in defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>; //===----------------------------------------------------------------------===// @@ -748,6 +752,7 @@ let isCommutable = 1 in defm MUL : SIMDBinaryFP<fmul, "mul", 156>; // Division: div +let Predicates = [HasSIMD128, HasUnimplementedSIMD] in defm DIV : SIMDBinaryFP<fdiv, "div", 157>; // NaN-propagating minimum: min |
