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authorWouter van Oortmerssen <aardappel@gmail.com>2019-02-05 01:19:45 +0000
committerWouter van Oortmerssen <aardappel@gmail.com>2019-02-05 01:19:45 +0000
commit1a91cb0402270a3ce77a9397abda655384d89a43 (patch)
treec55a16056aad9f18a9e8fde3934cac4409cf9a63 /llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
parent60731071dedd20ca77e2f53d17b148e25d3bf489 (diff)
downloadbcm5719-llvm-1a91cb0402270a3ce77a9397abda655384d89a43.tar.gz
bcm5719-llvm-1a91cb0402270a3ce77a9397abda655384d89a43.zip
[WebAssembly] Make disassembler always emit most canonical name.
Summary: There are a few instructions that all map to the same opcode, so when disassembling, we have to pick one. That was just the first one before (the except_ref variant in the case of "call"), now it is the one marked as IsCanonical in tablegen, or failing that, the shortest name (which is typically the "canonical" one). Also introduced a canonical "end" instruction for this purpose. Reviewers: dschuff, tlively Subscribers: sbc100, jgravelle-google, aheejin, llvm-commits, sunfish Tags: #llvm Differential Revision: https://reviews.llvm.org/D57713 llvm-svn: 353131
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td10
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index ab0f48c9a1e..71c469d755b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -125,12 +125,14 @@ defm "" : ConstVec<v8i16,
ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
"$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
+let IsCanonical = 1 in {
defm "" : ConstVec<v4i32,
- (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
+ (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
vec_i32imm_op:$i2, vec_i32imm_op:$i3),
- (build_vector (i32 imm:$i0), (i32 imm:$i1),
- (i32 imm:$i2), (i32 imm:$i3)),
- "$i0, $i1, $i2, $i3">;
+ (build_vector (i32 imm:$i0), (i32 imm:$i1),
+ (i32 imm:$i2), (i32 imm:$i3)),
+ "$i0, $i1, $i2, $i3">;
+}
defm "" : ConstVec<v2i64,
(ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
(build_vector (i64 imm:$i0), (i64 imm:$i1)),
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