summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/SIISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-111-9/+0
| | | | | | | This saves a second compare and an and / or by using the unordered comparison instructions. llvm-svn: 224066
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-2/+0
| | | | llvm-svn: 224065
* R600/SI: Use getTargetConstant in AdjustRegClassMarek Olsak2014-12-101-2/+2
| | | | llvm-svn: 223940
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-1/+6
| | | | llvm-svn: 223614
* R600/SI: Set correct number of user sgprs for HSA runtimeTom Stellard2014-12-021-1/+4
| | | | | | We don't support scratch buffers yet with HSA. llvm-svn: 223130
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-3/+7
| | | | llvm-svn: 223125
* R600/SI: Fix assertion on sign extend of 3 vectorsMatt Arsenault2014-11-281-2/+2
| | | | | | | This was trying to create an MVT with 3x vectors which created an invalid EVT llvm-svn: 222942
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-1/+1
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Make sure resource descriptors are always stored in SGPRsTom Stellard2014-11-181-2/+2
| | | | llvm-svn: 222253
* Convert some EVTs to MVTs where only a SimpleValueType is needed.Craig Topper2014-11-161-1/+1
| | | | llvm-svn: 222109
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-141-0/+68
| | | | llvm-svn: 222032
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-2/+1
| | | | llvm-svn: 222012
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-14/+0
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Move all rsrc building functions to SIISelLoweringMatt Arsenault2014-11-051-0/+44
| | | | llvm-svn: 221383
* R600/SI: Remove SI_ADDR64_RSRCMatt Arsenault2014-11-051-29/+54
| | | | llvm-svn: 221382
* R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGsMatt Arsenault2014-11-021-1/+2
| | | | llvm-svn: 221118
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-0/+5
| | | | llvm-svn: 220342
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-211-0/+9
| | | | llvm-svn: 220304
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-171-30/+0
| | | | | | | Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. llvm-svn: 220056
* Reapply "R600: Add new intrinsic to read work dimensions"Jan Vesely2014-10-141-2/+9
| | | | | | | | | This effectively reverts revert 219707. After fixing the test to work with new function name format and renamed intrinsic. Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219710
* Revert "R600: Add new intrinsic to read work dimensions"Rafael Espindola2014-10-141-9/+2
| | | | | | | | This reverts commit r219705. CodeGen/R600/work-item-intrinsics.ll was failing on linux. llvm-svn: 219707
* R600: Add new intrinsic to read work dimensionsJan Vesely2014-10-141-2/+9
| | | | | | | | | | | | | | v2: Add SI lowering Add test v3: Place work dimensions after the kernel arguments. v4: Calculate offset while lowering arguments v5: rebase v6: change prefix to AMDGPU Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219705
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-091-14/+12
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+29
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-031-3/+0
| | | | llvm-svn: 219038
* R600/SI: Also fix fsub + fadd a, a to mad combinesMatt Arsenault2014-09-291-0/+22
| | | | llvm-svn: 218609
* R600/SI: Fix using mad with multiplies by 2Matt Arsenault2014-09-291-0/+35
| | | | | | | | | These turn into fadds, so combine them into the target mad node. fadd (fadd (a, a), b) -> mad 2.0, a, b llvm-svn: 218608
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-261-58/+8
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Remove apparently dead code in legalizeOperandsMatt Arsenault2014-09-261-8/+0
| | | | | | | | No tests hit this, and I don't see any way a GlobalAddress node would survive beyond lowering on SI. It it would, the move should probably be inserted by selection. llvm-svn: 218526
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-11/+34
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-221-25/+55
| | | | llvm-svn: 218250
* R600/SI: Remove promotion of instructions to e64 forms.Matt Arsenault2014-09-171-57/+5
| | | | | | | | Instructions are now generally selected to the e64 forms originally, and shrunk down later. Rename foldOperands to legalizeOperands, since that's really most of what it tries to do. llvm-svn: 217959
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-6/+14
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600/SI: Fix assertion from copying a TargetGlobalAddressMatt Arsenault2014-09-081-1/+2
| | | | | | | | | | | | | Assert in scheduler from an inserted copy_to_regclass from a constant. This only seems to break sometimes when a constant initializer address is forced into VGPRs in a non-entry block. No test since the only case I've managed to hit only happens with a future patch, and that case will also not be a problem once scalar instructions are used in non-entry blocks. llvm-svn: 217380
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-081-18/+30
| | | | llvm-svn: 217379
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+37
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* Use BitVector instead of int in R600 SIISelLowering.Alexey Samsonov2014-08-271-3/+4
| | | | | | | int may not have enough bits in it, which was detected by UBSan bootstrap (it reported left shift by a too large constant). llvm-svn: 216579
* R600/SI: Wrap local memory pointer in AssertZExt on SITom Stellard2014-08-221-0/+12
| | | | | | | | | These pointers are really just offsets and they will always be less than 16-bits. Using AssertZExt allows us to use computeKnownBits to prove that these values are positive. We will use this information in a later commit. llvm-svn: 216277
* R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the functionTom Stellard2014-08-211-7/+0
| | | | | | This fixes a crash in an ocl conformance test. llvm-svn: 216219
* Silencing an MSVC warning about loop variable conflicting with a variable ↵Aaron Ballman2014-08-181-1/+1
| | | | | | from an outer scope. NFC. llvm-svn: 215888
* R600/SI: Move all fabs / fneg handling to patternsMatt Arsenault2014-08-151-89/+0
| | | | llvm-svn: 215749
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-151-4/+28
| | | | llvm-svn: 215748
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-151-1/+29
| | | | llvm-svn: 215747
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-1/+108
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* R600/SI: Implement isLegalAddressingModeMatt Arsenault2014-08-151-0/+43
| | | | | | | | | | | | | The default assumes that a 16-bit signed offset is used. LDS instruction use a 16-bit unsigned offset, so it wasn't being used in some cases where it was assumed a negative offset could be used. More should be done here, but first isLegalAddressingMode needs to gain an addressing mode argument. For now, copy most of the rest of the default implementation with the immediate offset change. llvm-svn: 215732
* R600/SI: Custom lower CONCAT_VECTORSTom Stellard2014-08-091-1/+3
| | | | | | | This will lower them using register copies rather than loads and stores to the stack. llvm-svn: 215270
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-2/+2
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-27/+26
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Fix formatting.Matt Arsenault2014-08-021-22/+28
| | | | | | Avoid weird line wrapping of BuildMI dest register. llvm-svn: 214608
* [SDAG] MorphNodeTo recursively deletes dead operands of the oldChandler Carruth2014-08-011-1/+3
| | | | | | | | | | | | | fromulation of the node, which isn't really the desired behavior from within the combiner or legalizer, but is necessary within ISel. I've added a hopefully helpful comment and fixed the only two places where this took place. Yet another step toward the combiner and legalizer not needing to use update listeners with virtual calls to manage the worklists behind legalization and combining. llvm-svn: 214574
OpenPOWER on IntegriCloud