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authorTom Stellard <thomas.stellard@amd.com>2014-10-09 19:06:00 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-10-09 19:06:00 +0000
commit3457a8495a08edbd7839bf7a1ee0fdd61f5f17c4 (patch)
treed06096e7084b9bc47e2c434fbe861d7f57c28006 /llvm/lib/Target/R600/SIISelLowering.cpp
parentddac7611eefbf4015cb93a94d58396767adbef26 (diff)
downloadbcm5719-llvm-3457a8495a08edbd7839bf7a1ee0fdd61f5f17c4.tar.gz
bcm5719-llvm-3457a8495a08edbd7839bf7a1ee0fdd61f5f17c4.zip
R600/SI: Legalize CopyToReg during instruction selection
The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
Diffstat (limited to 'llvm/lib/Target/R600/SIISelLowering.cpp')
-rw-r--r--llvm/lib/Target/R600/SIISelLowering.cpp26
1 files changed, 12 insertions, 14 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp
index 1a73d9bda58..49ac269998e 100644
--- a/llvm/lib/Target/R600/SIISelLowering.cpp
+++ b/llvm/lib/Target/R600/SIISelLowering.cpp
@@ -1920,28 +1920,26 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
}
}
-/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
-/// LLVM assumes that all INSERT_SUBREG inputs are registers.
-static void legalizeInsertSubreg(MachineSDNode *InsertSubreg,
- SelectionDAG &DAG) {
-
- assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
+/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
+/// with frame index operands.
+/// LLVM assumes that inputs are to these instructions are registers.
+void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
+ SelectionDAG &DAG) const {
SmallVector<SDValue, 8> Ops;
- for (unsigned i = 0; i < 2; ++i) {
- if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
- Ops.push_back(InsertSubreg->getOperand(i));
+ for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
+ if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
+ Ops.push_back(Node->getOperand(i));
continue;
}
- SDLoc DL(InsertSubreg);
+ SDLoc DL(Node);
Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
- InsertSubreg->getOperand(i).getValueType(),
- InsertSubreg->getOperand(i)), 0));
+ Node->getOperand(i).getValueType(),
+ Node->getOperand(i)), 0));
}
- DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
- InsertSubreg->getOperand(2));
+ DAG.UpdateNodeOperands(Node, Ops);
}
/// \brief Fold the instructions after selecting them.
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