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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-02 23:46:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-02 23:46:54 +0000 |
| commit | 7d858d87cded040a339be4cc8890aa97b6de1571 (patch) | |
| tree | e0932e9ef87f237bdc44f316dfa291f3938b421f /llvm/lib/Target/R600/SIISelLowering.cpp | |
| parent | eb49216bba6a8d00a67817951f98f85b43a8bbbf (diff) | |
| download | bcm5719-llvm-7d858d87cded040a339be4cc8890aa97b6de1571.tar.gz bcm5719-llvm-7d858d87cded040a339be4cc8890aa97b6de1571.zip | |
R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
llvm-svn: 221118
Diffstat (limited to 'llvm/lib/Target/R600/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index f306a3bf9f4..c2b60d190ec 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -1943,7 +1943,8 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, if (TII->isMIMG(Node->getMachineOpcode())) adjustWritemask(Node, DAG); - if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG) { + if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG || + Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) { legalizeTargetIndependentNode(Node, DAG); return Node; } |
