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path: root/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-338/+0
| | | | llvm-svn: 239657
* R600/SI: Remove M0Reg register classTom Stellard2015-05-121-1/+0
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)Tom Stellard2015-05-121-5/+8
| | | | | | | TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. llvm-svn: 237132
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-2/+2
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Fix SIFixSGPRCopies for copies to physical registersMatt Arsenault2014-12-031-1/+6
| | | | | | | This shows up when operands required to be passed in VCC are copied to. llvm-svn: 223208
* R600/SI: Remove incorrect assertionMatt Arsenault2014-12-031-5/+5
| | | | | | This can be a COPY to a physical register, such as VCC llvm-svn: 223207
* R600/SI: Fix suspicious indexingMatt Arsenault2014-12-031-5/+7
| | | | | | | | The loop is over the operands of an instruction, and checks the register with the sub reg index of the dest register. This probably meant to be checking the sub reg index of the same operand. llvm-svn: 223205
* R600/SI: Only use one DEBUG()Matt Arsenault2014-11-251-2/+1
| | | | llvm-svn: 222789
* R600/SI: Assume SIFixSGPRCopies makes changesMatt Arsenault2014-11-171-1/+2
| | | | | | I'm not sure if this was breaking anything. llvm-svn: 222174
* R600/SI: Simplify debug printingMatt Arsenault2014-10-171-5/+3
| | | | llvm-svn: 219999
* R600/SI: Move PHIs that define SGPRs to the VALU in most casesTom Stellard2014-09-241-0/+52
| | | | | | | This fixes a bug that is uncovered by a future commit and will be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case. llvm-svn: 218352
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-4/+4
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+3
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-151-7/+10
| | | | | | This prevents a future commit from regressing the load-i1.ll test. llvm-svn: 208887
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-301-1/+2
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-2/+2
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+10
| | | | llvm-svn: 205732
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-2/+2
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopiesTom Stellard2014-02-041-1/+1
| | | | | | | There is no lit test for this, because it would be too big and complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test. llvm-svn: 200775
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-2/+1
| | | | llvm-svn: 195026
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-3/+2
| | | | llvm-svn: 195025
* R600/SI: Remove redundant legalizeOperands callMatt Arsenault2013-11-141-1/+0
| | | | llvm-svn: 194749
* Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cppHans Wennborg2013-11-141-0/+1
| | | | | | This was casuing my release+asserts build on Windows to fail. llvm-svn: 194747
* Fix trailing whitespace in debug printingMatt Arsenault2013-11-141-1/+1
| | | | llvm-svn: 194683
* R600/SIFixSGPRCopies.cpp: Fix \param to \return. [-Wdocumentation]NAKAMURA Takumi2013-11-141-1/+1
| | | | llvm-svn: 194662
* Whitespace.NAKAMURA Takumi2013-11-141-4/+4
| | | | llvm-svn: 194661
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-17/+130
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600/SI: Fix another case of illegal VGPR to SGPR copyTom Stellard2013-08-221-1/+1
| | | | | | | | This fixes a crash in Unigine Tropics. https://bugs.freedesktop.org/show_bug.cgi?id=68389 llvm-svn: 189057
* R600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard2013-08-061-0/+152
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. llvm-svn: 187831
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