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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 20:59:25 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 20:59:25 +0000 |
| commit | 45c0b3a8828179519a66d98f0eb20170bd009744 (patch) | |
| tree | 338887688be7dc13eac18b976da27929e220a971 /llvm/lib/Target/R600/SIFixSGPRCopies.cpp | |
| parent | 842b4aecf87856a90cfcb4e3fa14fdb1dff32fcc (diff) | |
| download | bcm5719-llvm-45c0b3a8828179519a66d98f0eb20170bd009744.tar.gz bcm5719-llvm-45c0b3a8828179519a66d98f0eb20170bd009744.zip | |
R600/SI: Remove VReg_32 register class
Use VGPR_32 register class instead. These two register classes were
identical and having separate classes was causing
SIInstrInfo::isLegalOperands() to be overly conservative in some cases.
This change is necessary to prevent future paches from missing a folding
opportunity in fneg-fabs.ll.
llvm-svn: 225382
Diffstat (limited to 'llvm/lib/Target/R600/SIFixSGPRCopies.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index c7e008a8e5a..cd1b3acc5c8 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -235,8 +235,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { unsigned Reg = MI.getOperand(0).getReg(); const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, MI.getOperand(0).getSubReg()); - if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) { - MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass); + if (TRI->getCommonSubClass(RC, &AMDGPU::VGPR_32RegClass)) { + MRI.constrainRegClass(Reg, &AMDGPU::VGPR_32RegClass); } if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) |
