summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* [PowerPC] Cust lower fpext v2f32 to v2f64 from extract_subvector v4f32Nemanja Ivanovic2019-09-161-18/+41
* [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC re...Craig Topper2019-09-121-3/+3
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-101-4/+4
* [Alignment] Use Align for TargetLowering::MinStackArgumentAlignmentGuillaume Chatelet2019-09-101-1/+1
* [SelectionDAG] Remove ISD::FP_ROUND_INREGCraig Topper2019-09-091-1/+0
* [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignmentGuillaume Chatelet2019-09-061-2/+2
* [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignmentGuillaume Chatelet2019-09-061-1/+1
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-1/+1
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-6/+6
* [PowerPC] Expand v1i128 sminRoland Froese2019-08-231-4/+12
* [PowerPC] Add combined ELF ABI and 32/64 bit queries to the subtarget. [NFC]Sean Fertile2019-08-221-45/+47
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-42/+42
* [AIX] Add call lowering for parameters that could pass onto FPRsJason Liu2019-08-141-3/+21
* [AIX]Lowering global address for 32/64bit small/large code modelsXiangling Liao2019-08-131-18/+23
* [PowerPC] Fix ICE when truncating some vectorsQiu Chaofan2019-08-131-1/+3
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-4/+4
* recommit:[PowerPC] Eliminate loads/swap feeding swap/store for vector type by...Zi Xuan Wu2019-08-011-0/+72
* revert r367382 because buildbot failureZi Xuan Wu2019-07-311-71/+0
* [PowerPC] Eliminate loads/swap feeding swap/store for vector type by using bi...Zi Xuan Wu2019-07-311-0/+71
* [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming conven...Jason Liu2019-07-221-1/+1
* PowerPC/SPE: Fix load/store handling for SPEJustin Hibbits2019-07-171-0/+23
* [NFC]Fix IR/MC depency issue for function descriptor SDAG implementationDavid Tenty2019-07-101-44/+35
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-4/+6
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-031-0/+4
* [PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and othersJinsong Ji2019-06-271-1/+10
* [PowerPC] Mark FCOPYSIGN legal for FP vectorsNemanja Ivanovic2019-06-261-0/+2
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-52/+52
* PowerPC: Optimize SPE double parameter calling setupJustin Hibbits2019-06-171-38/+81
* [PowerPC] Set the innermost hot loop to align 32 bytesKang Zhang2019-06-151-0/+12
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-0/+1
* [CodeGen] Generic Hardware Loop SupportSam Parker2019-06-071-4/+4
* [PowerPC] Exploit the vector min/max instructionsNemanja Ivanovic2019-06-061-0/+18
* [AIX] Implement function descriptor on SDAGJason Liu2019-06-061-16/+45
* [AIX] Implement call lowering with parameters could pass onto GPRsJason Liu2019-06-061-15/+78
* Implement call lowering without parameters on AIXJason Liu2019-05-241-14/+84
* [PowerPC] [ISEL] select x-form instruction for unaligned offsetChen Zheng2019-05-221-8/+13
* [PowerPC] use more meaningful name - NFCChen Zheng2019-05-211-6/+7
* [PowerPC] custom lower `v2f64 fpext v2f32`Lei Huang2019-05-101-0/+57
* [PowerPC] Use the two-constant NR algorithm for refining estimatesNemanja Ivanovic2019-05-071-1/+3
* [PowerPC] Fix erroneous condition for converting uint-to-fp vector conversionNemanja Ivanovic2019-05-061-3/+2
* Avoid cppcheck operator precedence warnings. NFCI.Simon Pilgrim2019-05-031-2/+2
* [NFC][PowerPC] Return early if the element type is not byte-sized in combineB...Kang Zhang2019-05-021-0/+5
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-7/+5
* [PowerPC] Try harder to avoid load/move-to VSR for partial vector loadsRoland Froese2019-04-291-15/+36
* [PowerPC] Allow using initial-exec TLS with PICJoerg Sonnenberger2019-04-241-3/+10
* Add period at end of comment.Sean Fertile2019-04-241-1/+1
* [PowerPC] Fix wrong ElemSIze when calling isConsecutiveLS()Kang Zhang2019-04-181-1/+1
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-1/+1
* [PowerPC] Add the support for __builtin_setrnd()Kang Zhang2019-03-291-0/+131
* [PowerPC] Strength reduction of multiply by a constant by shift and add/sub i...Zi Xuan Wu2019-03-291-0/+86
OpenPOWER on IntegriCloud